SPRSP58B june 2022 – june 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1
PRODUCTION DATA
SIGNAL NAME [1] | PIN TYPE [2] | DESCRIPTION [3] | ALW PIN [4] | AMC PIN [4] |
---|---|---|---|---|
DDR0_ACT_n | O | DDRSS Activation Command | N6 | M1 |
DDR0_ALERT_n | IO | DDRSS Alert | R3 | N1 |
DDR0_CAS_n | O | DDRSS Column Address Strobe | M4 | J3 |
DDR0_PAR | O | DDRSS Command and Address Parity | T1 | M2 |
DDR0_RAS_n | O | DDRSS Row Address Strobe | M5 | K5 |
DDR0_WE_n | O | DDRSS Write Enable | N3 | J2 |
DDR0_A0 | O | DDRSS Address Bus | J1 | F5 |
DDR0_A1 | O | DDRSS Address Bus | J2 | G5 |
DDR0_A2 | O | DDRSS Address Bus | K3 | G4 |
DDR0_A3 | O | DDRSS Address Bus | L5 | H4 |
DDR0_A4 | O | DDRSS Address Bus | K4 | J5 |
DDR0_A5 | O | DDRSS Address Bus | K1 | H5 |
DDR0_A6 | O | DDRSS Address Bus | R2 | P4 |
DDR0_A7 | O | DDRSS Address Bus | P2 | N2 |
DDR0_A8 | O | DDRSS Address Bus | P1 | P2 |
DDR0_A9 | O | DDRSS Address Bus | P4 | N4 |
DDR0_A10 | O | DDRSS Address Bus | R5 | N3 |
DDR0_A11 | O | DDRSS Address Bus | P5 | M3 |
DDR0_A12 | O | DDRSS Address Bus | R6 | P5 |
DDR0_A13 | O | DDRSS Address Bus | R1 | N5 |
DDR0_BA0 | O | DDRSS Bank Address | M1 | L5 |
DDR0_BA1 | O | DDRSS Bank Address | N1 | L3 |
DDR0_BG0 | O | DDRSS Bank Group | T4 | L4 |
DDR0_BG1 | O | DDRSS Bank Group | N2 | L2 |
DDR0_CAL0 (1) | A | IO Pad Calibration Resistor | M2 | K4 |
DDR0_CK0 | O | DDRSS Clock | L1 | J1 |
DDR0_CK0_n | O | DDRSS Negative Clock | L2 | K1 |
DDR0_CKE0 | O | DDRSS Clock Enable | H2 | G3 |
DDR0_CKE1 | O | DDRSS Clock Enable | J4 | H2 |
DDR0_CS0_n | O | DDRSS Chip Select | L6 | H3 |
DDR0_CS1_n | O | DDRSS Chip Select | K2 | G1 |
DDR0_DM0 | IO | DDRSS Data Mask | H5 | E3 |
DDR0_DM1 | IO | DDRSS Data Mask | W5 | R4 |
DDR0_DQ0 | IO | DDRSS Data | F4 | C2 |
DDR0_DQ1 | IO | DDRSS Data | G5 | E4 |
DDR0_DQ2 | IO | DDRSS Data | F3 | D3 |
DDR0_DQ3 | IO | DDRSS Data | H6 | E5 |
DDR0_DQ4 | IO | DDRSS Data | E3 | D2 |
DDR0_DQ5 | IO | DDRSS Data | G2 | F3 |
DDR0_DQ6 | IO | DDRSS Data | F2 | F1 |
DDR0_DQ7 | IO | DDRSS Data | F1 | F2 |
DDR0_DQ8 | IO | DDRSS Data | U1 | R3 |
DDR0_DQ9 | IO | DDRSS Data | U3 | R2 |
DDR0_DQ10 | IO | DDRSS Data | U2 | T2 |
DDR0_DQ11 | IO | DDRSS Data | V5 | U2 |
DDR0_DQ12 | IO | DDRSS Data | W2 | U3 |
DDR0_DQ13 | IO | DDRSS Data | V6 | U4 |
DDR0_DQ14 | IO | DDRSS Data | Y1 | T4 |
DDR0_DQ15 | IO | DDRSS Data | W1 | T5 |
DDR0_DQS0 | IO | DDRSS Data Strobe | E1 | D1 |
DDR0_DQS0_n | IO | DDRSS Complimentary Data Strobe | E2 | E1 |
DDR0_DQS1 | IO | DDRSS Data Strobe | V1 | T1 |
DDR0_DQS1_n | IO | DDRSS Complimentary Data Strobe | V2 | R1 |
DDR0_ODT0 | O | DDRSS On-Die Termination for Chip Select 0 | H1 | J4 |
DDR0_ODT1 | O | DDRSS On-Die Termination for Chip Select 1 | J3 | K2 |
DDR0_RESET0_n | O | DDRSS Reset | G1 | G2 |