SPRSP58B june 2022 – june 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1
PRODUCTION DATA
This section describes connectivity requirements for package balls that have specific connectivity requirements and unused package balls.
All power balls must be supplied with the voltages specified in Section 7.5, Recommended Operating Conditions, unless otherwise specified .
For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be connected to these device ball numbers.
ALW BALL NUMBER |
AMC BALL NUMBER |
BALL NAME | CONNECTION REQUIREMENTS |
---|---|---|---|
D1 B10 |
B1 A11 |
MCU_ERRORn TRSTn |
Each of these balls must be connected to VSS through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic low level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-down can be used to hold a valid logic low level if no PCB signal trace is connected to the ball. |
E12 C11 E11 F20 A10 A11 B11 |
D9 B10 C9 E15 C10 D10 B11 |
EMU0 EMU1 MCU_RESETz RESET_REQz TCK TDI TMS |
Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high level if a PCB signal trace is connected and not actively driven by an attached device. The internal pull-up can be used to hold a valid logic high level if no PCB signal trace is connected to the ball. |
A8 D10 B9 A9 |
B9 A10 E9 A9 |
MCU_I2C0_SCL MCU_I2C0_SDA WKUP_I2C0_SCL WKUP_I2C0_SDA |
Each of these balls must be connected to the corresponding power supply(1) through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high level. |
M25 N23 N24 N25 P24 P22 P21 R23 R24 R25 T25 R21 T22 T24 U25 U24 |
K19 L19 L20 L21 M21 L17 L18 M20 N20 N21 M17 N18 N17 N19 P19 P20 |
GPMC0_AD0 GPMC0_AD1 GPMC0_AD2 GPMC0_AD3 GPMC0_AD4 GPMC0_AD5 GPMC0_AD6 GPMC0_AD7 GPMC0_AD8 GPMC0_AD9 GPMC0_AD10 GPMC0_AD11 GPMC0_AD12 GPMC0_AD13 GPMC0_AD14 GPMC0_AD15 |
Each of these balls must be connected to the corresponding power supply(1) or VSS through separate external pull resistors to ensure the inputs associated with these balls are held to a valid logic high or low level as appropriate to select the desired device boot mode. |
K9 L8 P9 R8 - - M9 |
K9 L8 J8 K7 C1 U1 L7 |
VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR VDDS_DDR_C |
If DDRSS is not used, each of these balls must be connected directly to VSS. |
N6 R3 M4 T1 M5 N3 J1 J2 K3 L5 K4 K1 R2 P2 P1 P4 R5 P5 R6 R1 M1 N1 T4 N2 M2 L1 L2 H2 J4 L6 K2 H5 W5 F4 G5 F3 H6 E3 G2 F2 F1 U1 U3 U2 V5 W2 V6 Y1 W1 E1 E2 V1 V2 H1 J3 G1 |
M1 N1 J3 M2 K5 J2 F5 G5 G4 H4 J5 H5 P4 N2 P2 N4 N3 M3 P5 N5 L5 L3 L4 L2 K4 J1 K1 G3 H2 H3 G1 E3 R4 C2 E4 D3 E5 D2 F3 F1 F2 R3 R2 T2 U2 U3 U4 T4 T5 D1 E1 T1 R1 J4 K2 G2 |
DDR0_ACT_n DDR0_ALERT_n DDR0_CAS_n DDR0_PAR DDR0_RAS_n DDR0_WE_n DDR0_A0 DDR0_A1 DDR0_A2 DDR0_A3 DDR0_A4 DDR0_A5 DDR0_A6 DDR0_A7 DDR0_A8 DDR0_A9 DDR0_A10 DDR0_A11 DDR0_A12 DDR0_A13 DDR0_BA0 DDR0_BA1 DDR0_BG0 DDR0_BG1 DDR0_CAL0 DDR0_CK0 DDR0_CK0_n DDR0_CKE0 DDR0_CKE1 DDR0_CS0_n DDR0_CS1_n DDR0_DM0 DDR0_DM1 DDR0_DQ0 DDR0_DQ1 DDR0_DQ2 DDR0_DQ3 DDR0_DQ4 DDR0_DQ5 DDR0_DQ6 DDR0_DQ7 DDR0_DQ8 DDR0_DQ9 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR0_DQS0 DDR0_DQS0_n DDR0_DQS1 DDR0_DQS1_n DDR0_ODT0 DDR0_ODT1 DDR0_RESET0_n |
If DDRSS is not used, leave unconnected.Note: The DDR0 pins in this list can only be left unconnected when VDDS_DDR and VDDS_DDR_C are connected to VSS. The DDR0 pins must be connected as defined in the DDR Board Design and Layout Guidelines, when VDDS_DDR and VDDS_DDR_C are connected to a power source. |
W12 Y11 Y13 |
P11 R11 R10 |
VDDA_CORE_USB VDDA_1P8_USB VDDA_3P3_USB |
USB0 and USB1 share these power rails, so each of these balls must be connected to valid power sources when either USB0 or USB1 is used.If USB0 and USB1 are not used, each of these balls must be connected directly to VSS. |
AE11 AD11 AE10 AC11 AD10 AE9 AC9 AB10 |
AA11 Y10 T8 V10 W8 W9 V9 U9 |
USB0_DM USB0_DP USB0_RCALIB USB0_VBUS USB1_DM USB1_DP USB1_RCALIB USB1_VBUS |
If USB0 or USB1 is not used, leave the respective DM, DP, and VBUS balls unconnected.Note: The USB0_RCALIB and USB1_RCALIB pins can only be left unconnected when VDDA_CORE_USB, VDDA_1P8_USB, and VDDA_3P3_USB are connected to VSS. The USB0_RCALIB and USB1_RCALIB pins must be connected to VSS through separate appropriate external resistors when VDDA_CORE_USB, VDDA_1P8_USB, and VDDA_3P3_USB are connected to power sources. |
W13 W14 |
P12 R12 |
VDDA_CORE_CSIRX0 VDDA_1P8_CSIRX0 |
If CSIRX0 is not used and the device boundary scan function is required, each of these balls must be connected to valid power sources.If CSIRX0 is not used and the device boundary scan function is not required, each of these balls can alternatively be connected directly to VSS. |
AD15 AE15 AB14 AC15 AD14 AE14 AD13 AE13 AB12 AC13 AA14 |
AA14 AA13 Y13 Y12 V13 V12 U12 U11 W12 W11 T11 |
CSI0_RXCLKN CSI0_RXCLKP CSI0_RXN0 CSI0_RXP0 CSI0_RXN1 CSI0_RXP1 CSI0_RXN2 CSI0_RXP2 CSI0_RXN3 CSI0_RXP3 CSI0_RXRCALIB |
If CSIRX0 is not used, leave unconnected. |
AA5 Y6 AD3 AB4 Y8 AA8 AB6 AA7 AC6 AC5 AE5 AD6 AE6 AD7 AD8 AE7 AD4 AE3 AE4 AD5 |
AA2 AA3 V5 V6 U7 U6 W6 W5 AA4 Y5 AA6 AA5 AA10 Y9 AA8 Y8 V7 V8 Y7 AA7 |
OLDI0_A0N OLDI0_A0P OLDI0_A1N OLDI0_A1P OLDI0_A2N OLDI0_A2P OLDI0_A3N OLDI0_A3P OLDI0_A4N OLDI0_A4P OLDI0_A5N OLDI0_A5P OLDI0_A6N OLDI0_A6P OLDI0_A7N OLDI0_A7P OLDI0_CLK0N OLDI0_CLK0P OLDI0_CLK1N OLDI0_CLK1P |
If OLDI0 is not used, leave unconnected. |
H10 | F6 | VMON_VSYS | If VMON_VSYS is not used, this ball must be connected directly to VSS. |
G10 K10 |
H9 K11 |
VMON_1P8_SOC VMON_3P3_SOC |
If VMON_1P8_SOC and VMON_3P3_SOC are not used to monitor the SOC power rails, these balls must still be connected to their respective 1.8V and 3.3V power rails. |
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This can be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors are recommended to hold a valid logic level on balls with external connections.
Many of the device IOs are turned off by default and external pull resistors may be required to hold inputs of any attached device in a valid logic state until software initializes the respective IOs. The state of configurable device IOs are defined in the BALL STATE DURING RESET RX/TX/PULL and BALL STATE AFTER RESET RX/TX/PULL columns of the Pin Attributes table. Any IO with its input buffer (RX) turned off is allowed to float without damaging the device. However, any IO with its input buffer (RX) turned on shall never be allowed to float to any potential between VILSS and VIHSS. The input buffer can enter a high-current state which could damage the IO cell if allowed to float between these levels.