SPRSP58B
june 2022 – june 2023
AM620-Q1
,
AM623
,
AM625
,
AM625-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
3.1
Functional Block Diagram
4
Revision History
5
Device Comparison
5.1
Related Products
6
Terminal Configuration and Functions
6.1
Pin Diagrams
6.2
Pin Attributes
12
13
6.3
Signal Descriptions
15
6.3.1
CPSW3G
6.3.1.1
MAIN Domain
18
19
20
21
6.3.2
CPTS
6.3.2.1
MAIN Domain
24
6.3.3
CSI-2
6.3.3.1
MAIN Domain
27
6.3.4
DDRSS
6.3.4.1
MAIN Domain
30
6.3.5
DSS
6.3.5.1
MAIN Domain
33
6.3.6
ECAP
6.3.6.1
MAIN Domain
36
37
38
6.3.7
Emulation and Debug
6.3.7.1
MAIN Domain
41
6.3.7.2
MCU Domain
43
6.3.8
EPWM
6.3.8.1
MAIN Domain
46
47
48
49
6.3.9
EQEP
6.3.9.1
MAIN Domain
52
53
54
6.3.10
GPIO
6.3.10.1
MAIN Domain
57
58
6.3.10.2
MCU Domain
60
6.3.11
GPMC
6.3.11.1
MAIN Domain
63
6.3.12
I2C
6.3.12.1
MAIN Domain
66
67
68
69
6.3.12.2
MCU Domain
71
6.3.12.3
WKUP Domain
73
6.3.13
MCAN
6.3.13.1
MAIN Domain
76
6.3.13.2
MCU Domain
78
79
6.3.14
MCASP
6.3.14.1
MAIN Domain
82
83
84
6.3.15
MCSPI
6.3.15.1
MAIN Domain
87
88
89
6.3.15.2
MCU Domain
91
92
6.3.16
MDIO
6.3.16.1
MAIN Domain
95
6.3.17
MMC
6.3.17.1
MAIN Domain
98
99
100
6.3.18
OLDI
6.3.18.1
MAIN Domain
103
6.3.19
OSPI
6.3.19.1
MAIN Domain
106
6.3.20
Power Supply
108
6.3.21
PRUSS
6.3.21.1
MAIN Domain
111
112
6.3.22
Reserved
114
6.3.23
System and Miscellaneous
6.3.23.1
Boot Mode Configuration
6.3.23.1.1
MAIN Domain
118
6.3.23.2
Clock
6.3.23.2.1
MCU Domain
121
6.3.23.2.2
WKUP Domain
123
6.3.23.3
System
6.3.23.3.1
MAIN Domain
126
6.3.23.3.2
MCU Domain
128
6.3.23.3.3
WKUP Domain
130
6.3.23.4
VMON
132
6.3.24
TIMER
6.3.24.1
MAIN Domain
135
6.3.24.2
MCU Domain
137
6.3.24.3
WKUP Domain
139
6.3.25
UART
6.3.25.1
MAIN Domain
142
143
144
145
146
147
148
6.3.25.2
MCU Domain
150
6.3.25.3
WKUP Domain
152
6.3.26
USB
6.3.26.1
MAIN Domain
155
156
6.4
Pin Connectivity Requirements
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings for Devices which are not AEC - Q100 Qualified
7.3
ESD Ratings for AEC - Q100 Qualified Devices in the AMC Package
7.4
Power-On Hours (POH)
7.5
Recommended Operating Conditions
7.6
Operating Performance Points
7.7
Power Consumption Summary
7.8
Electrical Characteristics
7.8.1
I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
7.8.2
Fail-Safe Reset (FS RESET) Electrical Characteristics
7.8.3
High-Frequency Oscillator (HFOSC) Electrical Characteristics
7.8.4
Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
7.8.5
SDIO Electrical Characteristics
7.8.6
LVCMOS Electrical Characteristics
7.8.7
OLDI LVDS (OLDI) Electrical Characteristics
7.8.8
CSI-2 (D-PHY) Electrical Characteristics
7.8.9
USB2PHY Electrical Characteristics
7.8.10
DDR Electrical Characteristics
7.9
VPP Specifications for One-Time Programmable (OTP) eFuses
7.9.1
Recommended Operating Conditions for OTP eFuse Programming
7.9.2
Hardware Requirements
7.9.3
Programming Sequence
7.9.4
Impact to Your Hardware Warranty
7.10
Thermal Resistance Characteristics
7.10.1
Thermal Resistance Characteristics for ALW and AMC Packages
7.11
Timing and Switching Characteristics
7.11.1
Timing Parameters and Information
7.11.2
Power Supply Requirements
7.11.2.1
Power Supply Slew Rate Requirement
7.11.2.2
Power Supply Sequencing
7.11.2.2.1
Power-Up Sequencing
7.11.2.2.2
Power-Down Sequencing
7.11.2.2.3
Partial IO Power Sequencing
7.11.3
System Timing
7.11.3.1
Reset Timing
7.11.3.2
Error Signal Timing
7.11.3.3
Clock Timing
7.11.4
Clock Specifications
7.11.4.1
Input Clocks / Oscillators
7.11.4.1.1
MCU_OSC0 Internal Oscillator Clock Source
7.11.4.1.1.1
Load Capacitance
7.11.4.1.1.2
Shunt Capacitance
7.11.4.1.2
MCU_OSC0 LVCMOS Digital Clock Source
7.11.4.1.3
WKUP_LFOSC0 Internal Oscillator Clock Source
7.11.4.1.4
WKUP_LFOSC0 LVCMOS Digital Clock Source
7.11.4.1.5
WKUP_LFOSC0 Not Used
7.11.4.2
Output Clocks
7.11.4.3
PLLs
7.11.4.4
Recommended System Precautions for Clock and Control Signal Transitions
7.11.5
Peripherals
7.11.5.1
CPSW3G
7.11.5.1.1
CPSW3G MDIO Timing
7.11.5.1.2
CPSW3G RMII Timing
7.11.5.1.3
CPSW3G RGMII Timing
7.11.5.2
CPTS
7.11.5.3
CSI-2
7.11.5.4
DDRSS
7.11.5.5
DSS
7.11.5.6
ECAP
7.11.5.7
Emulation and Debug
7.11.5.7.1
Trace
7.11.5.7.2
JTAG
7.11.5.8
EPWM
7.11.5.9
EQEP
7.11.5.10
GPIO
7.11.5.11
GPMC
7.11.5.11.1
GPMC and NOR Flash — Synchronous Mode
7.11.5.11.2
GPMC and NOR Flash — Asynchronous Mode
7.11.5.11.3
GPMC and NAND Flash — Asynchronous Mode
7.11.5.12
I2C
7.11.5.13
MCAN
7.11.5.14
MCASP
7.11.5.15
MCSPI
7.11.5.15.1
MCSPI — Controller Mode
7.11.5.15.2
MCSPI — Peripheral Mode
7.11.5.16
MMCSD
7.11.5.16.1
MMC0 - eMMC/SD/SDIO Interface
7.11.5.16.1.1
Legacy SDR Mode
7.11.5.16.1.2
High Speed SDR Mode
7.11.5.16.1.3
HS200 Mode
7.11.5.16.1.4
Default Speed Mode
7.11.5.16.1.5
High Speed Mode
7.11.5.16.1.6
UHS–I SDR12 Mode
7.11.5.16.1.7
UHS–I SDR25 Mode
7.11.5.16.1.8
UHS–I SDR50 Mode
7.11.5.16.1.9
UHS–I DDR50 Mode
7.11.5.16.1.10
UHS–I SDR104 Mode
7.11.5.16.2
MMC1/MMC2 - SD/SDIO Interface
7.11.5.16.2.1
Default Speed Mode
7.11.5.16.2.2
High Speed Mode
7.11.5.16.2.3
UHS–I SDR12 Mode
7.11.5.16.2.4
UHS–I SDR25 Mode
7.11.5.16.2.5
UHS–I SDR50 Mode
7.11.5.16.2.6
UHS–I DDR50 Mode
7.11.5.16.2.7
UHS–I SDR104 Mode
7.11.5.17
OLDI
7.11.5.17.1
OLDI0 Switching Characteristics
7.11.5.18
OSPI
7.11.5.18.1
OSPI0 PHY Mode
7.11.5.18.1.1
OSPI0 With PHY Data Training
7.11.5.18.1.2
OSPI0 Without Data Training
7.11.5.18.1.2.1
OSPI0 PHY SDR Timing
7.11.5.18.1.2.2
OSPI0 PHY DDR Timing
7.11.5.18.2
OSPI0 Tap Mode
7.11.5.18.2.1
OSPI0 Tap SDR Timing
7.11.5.18.2.2
OSPI0 Tap DDR Timing
7.11.5.19
PRUSS
7.11.5.19.1
PRUSS Programmable Real-Time Unit (PRU)
7.11.5.19.1.1
PRUSS PRU Direct Output Mode Timing
7.11.5.19.1.2
PRUSS PRU Parallel Capture Mode Timing
7.11.5.19.1.3
PRUSS PRU Shift Mode Timing
7.11.5.19.2
PRUSS Industrial Ethernet Peripheral (IEP)
7.11.5.19.2.1
PRUSS IEP Timing
7.11.5.19.3
PRUSS Universal Asynchronous Receiver Transmitter (UART)
7.11.5.19.3.1
PRUSS UART Timing
7.11.5.19.4
PRUSS Enhanced Capture Peripheral (ECAP)
7.11.5.19.4.1
PRUSS ECAP Timing
7.11.5.20
Timers
7.11.5.21
UART
7.11.5.22
USB
8
Detailed Description
8.1
Overview
8.2
Processor Subsystems
8.2.1
Arm Cortex-A53 Subsystem
8.2.2
Device/Power Manager
8.2.3
Arm Cortex-M4F
8.3
Accelerators and Coprocessors
8.3.1
Graphics Processing Unit (GPU)
8.3.2
Programmable Real-Time Unit Subsystem (PRUSS)
8.4
Other Subsystems
8.4.1
Dual Clock Comparator (DCC)
8.4.2
Data Movement Subsystem (DMSS)
8.4.3
Memory Cyclic Redundancy Check (MCRC)
8.4.4
Peripheral DMA Controller (PDMA)
8.4.5
Real-Time Clock (RTC)
8.5
Peripherals
8.5.1
Gigabit Ethernet Switch (CPSW3G)
8.5.2
Camera Streaming Interface Receiver (CSI_RX_IF)
8.5.3
DDR Subsystem (DDRSS)
8.5.4
Display Subsystem (DSS)
8.5.5
Enhanced Capture (ECAP)
8.5.6
Error Location Module (ELM)
8.5.7
Enhanced Pulse Width Modulation (EPWM)
8.5.8
Error Signaling Module (ESM)
8.5.9
Enhanced Quadrature Encoder Pulse (EQEP)
8.5.10
General-Purpose Interface (GPIO)
8.5.11
General-Purpose Memory Controller (GPMC)
8.5.12
Global Timebase Counter (GTC)
8.5.13
Inter-Integrated Circuit (I2C)
8.5.14
Modular Controller Area Network (MCAN)
8.5.15
Multichannel Audio Serial Port (MCASP)
8.5.16
Multichannel Serial Peripheral Interface (MCSPI)
8.5.17
Multi-Media Card Secure Digital (MMCSD)
8.5.18
Octal Serial Peripheral Interface (OSPI)
8.5.19
Timers
8.5.20
Universal Asynchronous Receiver/Transmitter (UART)
8.5.21
Universal Serial Bus Subsystem (USBSS)
9
Applications, Implementation, and Layout
9.1
Device Connection and Layout Fundamentals
9.1.1
Power Supply
9.1.1.1
Power Supply Designs
9.1.1.2
Power Distribution Network Implementation Guidance
9.1.2
External Oscillator
9.1.3
JTAG, EMU, and TRACE
9.1.4
Reset
9.1.5
Unused Pins
9.2
Peripheral- and Interface-Specific Design Information
9.2.1
DDR Board Design and Layout Guidelines
9.2.2
OSPI/QSPI/SPI Board Design and Layout Guidelines
9.2.2.1
No Loopback, Internal PHY Loopback, and Internal Pad Loopback
9.2.2.2
External Board Loopback
9.2.2.3
DQS (only available in Octal SPI devices)
9.2.3
USB VBUS Design Guidelines
9.2.4
System Power Supply Monitor Design Guidelines
9.2.5
High Speed Differential Signal Routing Guidance
9.2.6
Thermal Solution Guidance
10
Device and Documentation Support
10.1
Device Nomenclature
10.1.1
Standard Package Symbolization
10.1.2
Device Naming Convention
10.2
Tools and Software
10.3
Documentation Support
10.4
Support Resources
10.5
Trademarks
10.6
Electrostatic Discharge Caution
10.7
Glossary
11
Mechanical, Packaging, and Orderable Information
11.1
Packaging Information
Table 6-26 I2C0 Signal Descriptions
SIGNAL NAME [
1
]
PIN TYPE [
2
]
DESCRIPTION [
3
]
ALW PIN [
4
]
AMC PIN [
4
]
I2C0_SCL
IOD
I2C Clock
B16
E12
I2C0_SDA
IOD
I2C Data
A16
D14