SPRSP58B june 2022 – june 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1
PRODUCTION DATA
Table 7-75, Figure 7-63, Table 7-76, and Figure 7-64 present timing requirements and switching characteristics for SPI – Controller Mode.
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SM4 | tsu(POCI-SPICLK) | Setup time, SPIn_D[x] valid before SPIn_CLK active edge | 2.8 | ns | |
SM5 | th(SPICLK-POCI) | Hold time, SPIn_D[x] valid after SPIn_CLK active edge | 3 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
SM1 | tc(SPICLK) | Cycle time, SPIn_CLK | 20 | ns | ||
SM2 | tw(SPICLKL) | Pulse duration, SPIn_CLK low | 0.5P - 1(1) | ns | ||
SM3 | tw(SPICLKH) | Pulse duration, SPIn_CLK high | 0.5P - 1(1) | ns | ||
SM6 | td(SPICLK-PICO) | Delay time, SPIn_CLK active edge to SPIn_D[x] | -3 | 2.5 | ns | |
SM7 | td(CS-PICO) | Delay time, SPIn_CSi active edge to SPIn_D[x] | 5 | ns | ||
SM8 | td(CS-SPICLK) | Delay time, SPIn_CSi active to SPIn_CLK first edge | PHA = 0 | B - 4 (3) | ns | |
PHA = 1 | A - 4 (2) | ns | ||||
SM9 | td(SPICLK-CS) | Delay time, SPIn_CLK last edge to SPIn_CSi inactive | PHA = 0 | A - 4(2) | ns | |
PHA = 1 | B - 4(3) | ns |