SPRSP58B june 2022 – june 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1
PRODUCTION DATA
Table 7-63 and Table 7-64 present timing requirements and switching characteristics for GPMC and NOR Flash - Synchronous Mode.
NO. | PARAMETER | DESCRIPTION | MODE(4) | MIN | MAX | MIN | MAX | UNIT |
---|---|---|---|---|---|---|---|---|
GPMC_FCLK = 100 MHz(1) | GPMC_FCLK = 133 MHz(1) | |||||||
F12 | tsu(dV-clkH) | Setup time, input data GPMC_AD[15:0] valid before output clock GPMC_CLK high | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
1.61 | 0.92 | ns | ||
not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
0.86 | 3.41 | ns | |||||
F13 | th(clkH-dV) | Hold time, input data GPMC_AD[15:0] valid after output clock GPMC_CLK high | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
2.09 | 2.09 | ns | ||
not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
2.09 | 2.09 | ns | |||||
F21 | tsu(waitV-clkH) | Setup time, input wait GPMC_WAIT[j](2)(3) valid before output clock GPMC_CLK high | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
1.61 | 0.92 | ns | ||
not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
0.86 | 3.41 | ns | |||||
F22 | th(clkH-waitV) | Hold time, input wait GPMC_WAIT[j](2)(3) valid after output clock GPMC_CLK high | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
2.09 | 2.09 | ns | ||
not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
2.09 | 2.09 | ns |
NO.(2) | PARAMETER | DESCRIPTION | MODE(16) | MIN | MAX | MIN | MAX | UNIT |
---|---|---|---|---|---|---|---|---|
100 MHz | 133 MHz | |||||||
F0 | 1 / tc(clk) | Period, output clock GPMC_CLK(15) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
10.00 | 7.52 | ns | ||
F1 | tw(clkH) | Typical pulse duration, output clock GPMC_CLK high | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
0.475P - 0.3(14) | 0.475P - 0.3(14) | ns | ||
F1 | tw(clkL) | Typical pulse duration, output clock GPMC_CLK low | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
0.475P - 0.3(14) | 0.475P - 0.3(14) | ns | ||
F2 | td(clkH-csnV) | Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition(13) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay |
F - 2.2 (5) | F + 3.75 | F - 2.2 (5) | F + 3.75 | ns |
F3 | td(clkH-CSn[i]V) | Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid(13) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay |
E - 2.2 (4) | E + 3.18 | E - 2.2 (4) | E + 4.5 | ns |
F4 | td(aV-clk) | Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
B - 2.3 (2) | B + 4.5 | B - 2.3 (2) | B + 4.5 | ns |
F5 | td(clkH-aIV) | Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
-2.3 | 4.5 | -2.3 | 4.5 | ns |
F6 | td(be[x]nV-clk) | Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
B - 2.3 (2) | B + 1.9 | B - 2.3 (2) | B + 1.9 | ns |
F7 | td(clkH-be[x]nIV) | Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid(10) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
D - 2.3(3) | D + 1.9 | D - 2.3 (3) | D + 1.9 | ns |
F7 | td(clkL-be[x]nIV) | Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(11) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
D - 2.3 (3) | D + 1.9 | D - 2.3 (3) | D + 1.9 | ns |
F7 | td(clkL-be[x]nIV). | Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
D - 2.3 (3) | D + 1.9 | D - 2.3 (3) | D + 1.9 | ns |
F8 | td(clkH-advn) | Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay |
G - 2.3(6) | G + 4.5 | G - 2.3 (6) | G + 4.5 | ns |
F9 | td(clkH-advnIV) | Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay |
D - 2.3 (3) | D + 4.5 | D - 2.3 (3) | D + 4.5 | ns |
F10 | td(clkH-oen) | Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay |
H - 2.3 (7) | H + 3.5 | H - 2.3 (7) | H + 3.5 | ns |
F11 | td(clkH-oenIV) | Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay |
H - 2.3 (7) | H + 3.5 | H - 2.3 (7) | H + 3.5 | ns |
F14 | td(clkH-wen) | Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay |
I - 2.3 (8) | I + 4.5 | I - 2.3 (8) | I + 4.5 | ns |
F15 | td(clkH-do) | Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(10) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
J - 2.3 (9) | J + 2.7 | J - 2.3 (9) | J + 2.7 | ns |
F15 | td(clkL-do) | Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(11) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
J - 2.3 (9) | J + 2.7 | J - 2.3 (9) | J + 2.7 | ns |
F15 | td(clkL-do). | Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
J - 2.3 (9) | J + 2.7 | J - 2.3 (9) | J + 2.7 | ns |
F17 | td(clkH-be[x]n) | Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(10) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
J - 2.3 (9) | J + 1.9 | J - 2.3 (9) | J + 1.9 | ns |
F17 | td(clkL-be[x]n) | Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(11) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
J - 2.3 (9) | J + 1.9 | J - 2.3 (9) | J + 1.9 | ns |
F17 | td(clkL-be[x]n). | Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12) | div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 |
J - 2.3 (9) | J + 1.9 | J - 2.3 (9) | J + 1.9 | ns |
F18 | tw(csnV) | Pulse duration, output chip select GPMC_CSn[i](13) low | Read | A | A | ns | ||
Write | A | A | ns | |||||
F19 | tw(be[x]nV) | Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low | Read | C | C | ns | ||
Write | C | C | ns | |||||
F20 | tw(advnV) | Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE low | Read | K | K | ns | ||
Write | K | K | ns |