SPRSP58B june 2022 – june 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1
PRODUCTION DATA
Table 7-99, Figure 7-83, Table 7-100, and Figure 7-84 present timing requirements and switching characteristics for MMC0 – Default Speed Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
DS1 | tsu(cmdV-clkH) | Setup time, MMC0_CMD valid before MMC0_CLK rising edge | 2.15 | ns | |
DS2 | th(clkH-cmdV) | Hold time, MMC0_CMD valid after MMC0_CLK rising edge | 1.67 | ns | |
DS3 | tsu(dV-clkH) | Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge | 2.15 | ns | |
DS4 | th(clkH-dV) | Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge | 1.67 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC0_CLK | 25 | MHz | ||
DS5 | tc(clk) | Cycle time, MMC0_CLK | 40 | ns | |
DS6 | tw(clkH) | Pulse duration, MMC0_CLK high | 18.7 | ns | |
DS7 | tw(clkL) | Pulse duration, MMC0_CLK low | 18.7 | ns | |
DS8 | td(clkL-cmdV) | Delay time, MMC0_CLK falling edge to MMC0_CMD transition | - 1.8 | 2.2 | ns |
DS9 | td(clkL-dV) | Delay time, MMC0_CLK falling edge to MMC0_DAT[3:0] transition | - 1.8 | 2.2 | ns |