SPRSP58B june 2022 – june 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1
PRODUCTION DATA
Table 7-81, Figure 7-67, Table 7-82, and Figure 7-68 present timing requirements and switching characteristics for MMC0 – Legacy SDR Mode.
NO. | IO Operating Voltage |
MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
LSDR1 | tsu(cmdV-clkH) | Setup time, MMC0_CMD valid before MMC0_CLK rising edge | 1.8 V | 4.2 | ns | |
3.3 V | 2.15 | ns | ||||
LSDR2 | th(clkH-cmdV) | Hold time, MMC0_CMD valid after MMC0_CLK rising edge | 1.8 V | 0.87 | ns | |
3.3 V | 1.67 | ns | ||||
LSDR3 | tsu(dV-clkH) | Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge | 1.8 V | 4.2 | ns | |
3.3 V | 2.15 | ns | ||||
LSDR4 | th(clkH-dV) | Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge | 1.8 V | 0.87 | ns | |
3.3 V | 1.67 | ns |
NO. | PARAMETER | IO Operating Voltage |
MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC0_CLK | 25 | MHz | |||
LSDR5 | tc(clk) | Cycle time, MMC0_CLK | 40 | ns | ||
LSDR6 | tw(clkH) | Pulse duration, MMC0_CLK high | 18.7 | ns | ||
LSDR7 | tw(clkL) | Pulse duration, MMC0_CLK low | 18.7 | ns | ||
LSDR8 | td(clkL-cmdV) | Delay time, MMC0_CLK falling edge to MMC0_CMD transition | 1.8 V | -2.1 | 2.1 | ns |
3.3 V | -1.8 | 2.2 | ns | |||
LSDR9 | td(clkL-dV) | Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition | 1.8 V | -2.1 | 2.1 | ns |
3.3 V | -1.8 | 2.2 | ns |