SPRUHJ1I January 2013 – October 2021 TMS320F2802-Q1 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F2806-Q1 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1
The third decimation rate is to execute the estimator inside of InstaSPIN, also known as the FAST™ algorithm. This is one of the most popular tick rates available in InstaSPIN since it decimates the most time consuming part of InstaSPIN, which is the FAST estimator. As shown in the previous tick rate that decimates the current controllers, this tick rate decimates the estimator execution. To show an example of how this is cascaded from the InstaSPIN execution clock, consider Figure 10-18. It shows an ISR per CTRL tick rate of 1, a CTRL per CURRENT tick rate of 2, and a CTRL per EST tick rate of 2 as well. This shows how several tick rates can be combined to achieve a desired CPU bandwidth, and it also shows dependencies of other clocks within InstaSPIN.
Figure 10-19 represents the values of this timing diagram in highlighted boxes.