SPRUHJ1I January 2013 – October 2021 TMS320F2802-Q1 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F2806-Q1 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1
The second tick rate to be discussed is the controller tick per current tick. This tick rate is used to slow down the current controllers with respect to the InstaSPIN execution rate. This tick rate only reduces the rate at which the current controllers are executed, which doesn't really help alleviate the CPU loading since there are only two PI controllers. It does reduce the current control performance though, so it is recommended to keep this tick rate equal to one, which means that the current controllers will be executed at the same rate as InstaSPIN execution. In order to show an example of how this tick rate can be used, consider the Figure 10-16. Also in this example we have chosen an ISR tick per CTRL tick rate of 3 to show how the CTRL per current tick is cascaded from the first tick rate.
Figure 10-17 shows the values for this example in highlighted boxes.