SPRUHJ1I January 2013 – October 2021 TMS320F2802-Q1 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F2806-Q1 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1
Decimation defines the number of ticks between module execution.
Controller clock tick (CTRL) is the main clock used for all timing in the software.
Typically the PWM Frequency triggers (can be decimated by the ePWM hardware for less overhead) an ADC SOC.
ADC SOC triggers an ADC Conversion Done.
ADC Conversion Done triggers ISR.
This relates the hardware ISR rate to the software controller rate.
Typcially want to consider some form of decimation (ePWM hardware, CURRENT or EST) over 16kHz ISR to insure interrupt completes and leaves time for background tasks.