SPRUHJ1I January 2013 – October 2021 TMS320F2802-Q1 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F2806-Q1 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1
For this example, consider the following scenario:
SpinTAC Velocity Plan is used to generate a motion sequence between 4 states (see Figure 9-9). Note that in this example, both the Plan functions STVELPLAN_run and STVELPLAN_runTick are being run from the ISR. In a final implementation, STVELPLAN_run can be run from a slower ISR or background loop.
The maximum cycles for STVELPLAN_run are contributed either by the Condition FSM state or the Transition FSM state but never both at the same time.
If the code is running in RAM, then Maximum cycles = 374 (fixed cycles for Condition FSM state) + (Number of Transitions * 274) + (Number of EXIT actions * 334).
The example plan in Figure 9-9 configures three transitions leaving State 0. All transitions check conditions that compare variables with variables (worst case), and 2 EXIT actions are configured to this state. So the maximum cycles occurs when the last transition is taken = 374 + (3 * 274) + (2 * 334) = 1864.
If the code is running in RAM, then Maximum cycles = 229 (fixed cycles for Transition FSM state) + Number of ENTER actions * 378.
The above example shows the State3 having 3 ENTER actions. This will cause the Transition FSM State to have maximum cycles = 229 + (3 * 378) = 1368.
Compare the two cases that can cause maximum cycles for STVELPLAN_run. In this instance, the maximum possible cycles are 1330, contributed by the Condition FSM state. Use that value as the worst case when calculating the percentage of CPU used by the interrupt.
The percentage of CPU used by the interrupt is calculated, where:
The previous calculation is where the main component of SpinTAC Velocity Plan is being ran from the ISR. When SpinTAC Velocity Plan is called from the background loop, the percentage of CPU used by the interrupt is calculated: