SPRUHJ1 User guide

SPRUHJ1I January 2013 – October 2021 TMS320F2802-Q1 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F2806-Q1 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1

9.1 InstaSPIN™ Software Execution Clock Tree

There are several clock decimations when using InstaSPIN. The first clock that needs to be considered is the interrupt clock, which is generated by a peripheral clocked with the CPU clock. Typically, the interrupt service routine (ISR) is triggered by the end of conversion (EOC) of the ADC. This conversion is triggered by the PWM module.

First of all, let us review how the PWM frequency is configured based on user's parameters from user.h. Starting from the CPU clock, user defines, in MHz, what the CPU clock rate is:

//! \brief Defines the system clock frequency, MHz (6xF and 6xM devices)
//!
#define USER_SYSTEM_FREQ_MHz       (90)
//! \brief Defines the system clock frequency, MHz (2xF devices)
//!
#define USER_SYSTEM_FREQ_MHz       (60)

Then, the PWM frequency in kHz is defined, which results in the interrupt frequency.

//! \brief Defines the Pulse Width Modulation (PWM) frequency, kHz 
//! 
#define USER_PWM_FREQ_kHz          (15.0) 
//! \brief Defines the Pulse Width Modulation (PWM) period, usec 
//! 
#define USER_PWM_PERIOD_usec      (1000.0/USER_PWM_FREQ_kHz) 
//! \brief Defines the Interrupt Service Routine (ISR) frequency, Hz 
//! 
#define USER_ISR_FREQ_Hz           (USER_PWM_FREQ_kHz *1000.0) 
//! \brief Defines the Interrupt Service Routine (ISR) period, usec 
//! 
#define USER_ISR_PERIOD_usec       USER_PWM_PERIOD_usec

So far, the CPU clock sets the PWM frequency, which also sets the frequency of the ISR. Now the ISR is actually not triggered by the PWM timer itself, but it is triggered by the end of conversion of the ADC which was started by the PWM timer.

Figure 10-1 is a timing diagram of the clocks from the CPU all the way to the ISR generation.

This timing diagram represents the interrupt triggering scenario that Texas Instruments delivers for InstaSPIN software package because this is the safest way the conversions will be ready when fetching the interrupt. Other scenarios might be considered by the user, such as ADC early interrupt, PWM interrupt or CPU timer interrupt. The only requirement is that those interrupts are generated at a fixed period.

Note that the execution time can be measured in several different ways. Here are some examples on how to measure execution time:

GPIO Toggle. An easy but not so accurate execution time measurement is to simply set a GPIO at the very beginning of the code to be measured and the clearing the same GPIO right after it. This method is very graphical since it can be displayed in a scope, and sine the interrupts are periodic, it will give a good trigger for the scope to measure execution time. The time can then be converted to CPU cycles if needed. One thing to consider using this method though is the time it takes for a particular architecture to set and clear a GPIO, as well as the interrupt fetch and return times.
CPU Timer Capture. A much more accurate execution time measurement is with a CPU timer. This can be done by running a CPU timer at the same clock as the CPU clock, with no prescaler or postcaler, and then read the timer after the code has been executed. This will give us the CPU cycles needed to execute the code of interest.

Figure 9-1 Clock Timing - CPU to ISR Generation

From the InstaSPIN execution timing, there are several decimation values, also known as tick rates that allow different execution clock rates for different portions of control code within InstaSPIN. The following tick rates are available for InstaSPIN:

//! \brief Defines the number of pwm clock ticks per isr clock tick
//!        Note: Valid values are 1, 2 or 3 only
#define USER_NUM_PWM_TICKS_PER_ISR_TICK       (1)
//! \brief Defines the number of isr ticks per controller clock tick 
//! 
#define USER_NUM_ISR_TICKS_PER_CTRL_TICK      (1) 
//! \brief Defines the number of controller clock ticks per current controller clock tick 
//! 
#define USER_NUM_CTRL_TICKS_PER_CURRENT_TICK  (1) 
//! \brief Defines the number of controller clock ticks per estimator clock tick 
//! 
#define USER_NUM_CTRL_TICKS_PER_EST_TICK      (1) 
//! \brief Defines the number of controller clock ticks per speed controller clock tick 
//! 
#define USER_NUM_CTRL_TICKS_PER_SPEED_TICK  (10) 
//! \brief Defines the number of controller clock ticks per trajectory clock tick 
//! 
#define USER_NUM_CTRL_TICKS_PER_TRAJ_TICK   (10)

In order to show all these tick rates, see Figure 10-2. The following acronyms are defined for easier reference within the software execution clock tree diagram:

USER_NUM_PWM_TICKS_PER_ISR_TICK -> /ETPS

USER_NUM_ISR_TICKS_PER_CTRL_TICK -> /ISRvsCTRL

USER_NUM_CTRL_TICKS_PER_CURRENT_TICK -> /CTRLvsCURRENT

USER_NUM_CTRL_TICKS_PER_EST_TICK -> /CTRLvsEST

USER_NUM_CTRL_TICKS_PER_SPEED_TICK -> /CTRLvsSPEED

USER_NUM_CTRL_TICKS_PER_TRAJ_TICK -> /CTRLvsTRAJ

In the case of the F2806x device, the software execution clock tree starts with a SYSCLKOUT of 90 MHz, and everything else is decimated from that clock. For the F2805x amd F2802x devices, the maximum frequency is 60 MHz, instead of 90 MHz.

After a clock prescaler, which is set to one by default, to get the best resolution of the PWM generator, we have the TBPRD register (see Figure 10-2). This register has a period value so that the output creates the PWM frequency.

Figure 9-2 Software Execution Clock Tree

The first decimation of the software execution clock tree is in hardware. Depending on the value of the ETPS register (Event Trigger Prescale Register), the PWM frequency can be divided 1, 2 or 3 times. This is useful when the ADC start of conversion signal needs to be triggered every PWM cycle, or every 2 or every 3 PWM cycles. This hardware decimation is controlled by the USER_NUM_PWM_TICKS_PER_ISR_TICK definition in user.h.

The second decimation block is done in software and will be explained in detail in the following section.