SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
An interrupt-enable bit must be set in the MMCi.MMCHS_IE register to enable the module internal source of interrupt.
When an interrupt event occurs, the single interrupt line is asserted and the LH must:
In the MMCi.MMCHS_STAT register, the card interrupt (CIRQ) and error interrupt (ERRI) bits cannot be cleared.
The MMCi.MMCHS_STAT[8] CIRQ status bit must be masked by disabling the MMCi.MMCHS_IE[8] CIRQ_ENABLE bit (set to 0x0), and then the interrupt routine must clear the SDIO interrupt source in the SDIO card common control register (CCCR).
The MMCi.MMCHS_STAT[15] ERRI bit is automatically cleared when all status bits in the MMCi.MMCHS_STATregister (bits 31 through 16) are cleared.