SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
During normal operation, the DDR controller may modify the FSP mode register values in memory. To do this, the user should program the DDRSS_CTL_164[1-0] MRW_DFS_UPDATE_FRC field with the frequency set that the DDR controller is using and program the appropriate new values in the FSP-related mode registers previously listed. Since there are two copies of each of these mode registers in the memory device (other than MR13), the user should also identify the appropriate frequency set points for operation and writing in the DDRSS_CTL_192[16] FSP_OP_CURRENT and DDRSS_CTL_192[24] FSP_WR_CURRENT bits.
Generally, the user should not modify the mode registers for the frequency set being used, and therefore should program the DDRSS_CTL_192[24] FSP_WR_CURRENT with the opposite value of the DDRSS_CTL_192[16] FSP_OP_CURRENT bit.
Once established the values to write, the frequency set in the DDR controller to use, and the frequency set points, the user should program the DDRSS_CTL_159[26-0] WRITE_MODEREG field for the operation:
When the DDRSS_CTL_159[26-0] WRITE_MODEREG field is written with bit [26] set to 1h, the corresponding MR13 mode register is updated automatically with the value in the DDRSS_CTL_180[7-0] MR13_DATA_0 or DDRSS_CTL_187[23-16] MR13_DATA_1 fields, except that the value in the DDRSS_CTL_192[24] FSP_WR_CURRENT bit will define the value written in MR13 [6] and the value in the DDRSS_CTL_192[16] FSP_OP_CURRENT bit will define the value written in MR13 [7]. This write occurs before the other mode register writes, which means that the user may inadvertently write the wrong frequency set point mode or switch to the new frequency set point.