SPRUIV7B May 2022 – September 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The debug/state registers are supplied to give software applications additional information about the PDMA than they would need in regular operation, but which may be useful in debug situations. The registers appear on the PSI-L bus, near the static TR registers. For receive, they are defined as in Table 11-88.
Name | PSIL Addr | Field | Description |
---|---|---|---|
Z* | 0x402 | 31:16 | This field holds the lower 12 bits of the current Z count for legacy pursposes. See register 0x40F below for the full width version of Z. |
Y | 0x402 | 15:0 | This field holds the current Y count. In X-Y FIFO mode, this is the number of X sized samples yet to be read from the peripheral for the DMA event being serviced. In MCAN mode, this field holds the next read offset to use when read to the CAN RX buffer. |
InEvent | 0x403 | 31 | When set, the PDMA is in the middle of processing a FIFO event. |
Tdown | 0x403 | 30 | When set, the PDMA is processing a teardown operation. This bit is set simultaneously with the teardown bit in the source (RX) RT enable register. This bit will clear when the teardown is complete, regardless as to if the teardown bit in the pairing register is cleared or not. The teardown will propagate to the UDMA-P and its full completion status can be checked there. |
Pause | 0x403 | 29 | When set, the PDMA is stopped in a paused state. This bit will clear if the channel is un-paused or disabled. |
Space | 0x403 | 28 | When set, there is a non-zero amount of internal FIFO space available to hold new read data. |
XSpace | 0x403 | 27 | When set, there is a enough internal FIFO space available to start servicing a peripheral DMA event. |
Buffer | 0x403 | 26 | This is the current RX buffer (0/1) for the current MCAN receive operation. |
State | 0x403 | 23:20 | This code reflects the current state of the PDMA channel, and is specific to the current implementation. |
EventCnt | 0x403 | 19:16 | This field holds the number of backlogged DMA events yet to be serviced. |
Z | 0x40F | 31:0 | This field holds the full width value of the current Z count. In X-Y FIFO mode, this field holds the 1 based FIFO count of the FIFO being currently read, or the number of FIFO completions when the current operation completes. In MCAN mode, this field holds the zero based buffer index of the buffer currently being read, or the number of previously completed buffers. |