SPRUIV7B May 2022 – September 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Some of the timers features described in this section may not be supported on this family of devices. For more information, see Timers Not Supported Features.
If the TIMER_TIOCP_CFG[3-2] IDLEMODE bit field sets the smart-idle mode or smart-idle with wake-up mode, the timer evaluates its internal capability to have the interface clock switched off. When there is no further internal activity (no pending interrupt sources: match, overflow, or timer capture events), the clock stop acknowledge signal is asserted and the timer enters sleep mode, ready to issue a wake-up request if configured in smart-idle with wake-up mode.
Figure 12-424 shows the wake-up request generation.
The timer wake-up-enable register allows masking of the expected source of the wake-up event that generates a wake-up request. The register is synchronously programmed with the interface clock before the Clock magagemet sends a clock stop request. The expected source of the wake-up event is an overflow (TIMER_TCRR), a timer match (the compare result of TIMER_TCRR and TIMER_TMAR matches the counter value), and a timer capture (detection of an external pulse transition of the correct polarity on the TIMER_PIEVENTCAPT).
When the wake-up event is issued, the associated interrupt status bit is set in the timer status register (TIMER_IRQSTATUS). The pending wake-up event is reset when the set status bit is overwritten with 1.
The status bit must be reset to re-enter idle mode.