SPRUIV7B May 2022 – September 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
The SoC memory map is constructed to enable using a larger MMU page to be 64KB and above. The system resource which can be owned by each individual software process is put at 64KB aligned memory boundary to provide the isolation among processes through MMU. Most of the simple end point peripherals are put at 64KB boundary for this purpose. The following are a few exceptions.
The debugSS_wrap contains multiple small mregions than 64KB. The main use case is to have a single SW process will own debug configuration.
GPIO modules are another exception. Each LVCMOS pin for SoC can be configured as a GPIO pin. Currently each GPIO module can provide up to 144 GPIO pins. The main domain and wkupmcu domain have separate LVCMOS IO control. In the main domain, it requires two GPIO modules to cover all the LVCMOS pins. These two GPIO modules are treated as a single entity from software point of view and these two GPIO modules are put at 4KB boundary instead of 64KB.
On the mcu domain, only one GPIO module needed to cover all the LVCMOS pins.
SoC also contains multiple DCC modules, and they are put at back to back on the memory map instead of spacing out at 64KB boundary. The reason is that DCC modules should be owned by a single safety processor.
Firewall and Initiator Secure Control(ISC) configurations are not on 64KB boundary. The configuration for those three items is at 1KB boundary, since the security initiator owns the configuration for them. QoS block is also put at 1KB boundary instead of 64KB, since the device manager owns the configuration of the QoS block.