SPRUIY2 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
      3. 3.2.3 RTINT (Real Time Interrupt)
      4. 3.2.4 INT (Low-Priority Interrupt)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Pipeline
    1. 4.1  Introduction
    2. 4.2  Decoupled Pipeline Phases
    3. 4.3  Dual Instruction Prefetch Buffers
    4. 4.4  Pipeline Advancement and Stalls
    5. 4.5  Pipeline Hazards and Protection Mechanisms
    6. 4.6  Register Updates and Corresponding Pipeline Phases
    7. 4.7  Register Reads and Writes During Normal Operation
    8. 4.8  D2 Read Protection
    9. 4.9  E1 Read Protection
    10. 4.10 WAW Protection
    11. 4.11 Protection During Interrupt
  7. 5Addressing Modes
    1. 5.1 Addressing Modes Overview
      1. 5.1.1 Documentation and Implementation
      2. 5.1.2 List of Addressing Mode Types
        1. 5.1.2.1 Additional Types of Addressing
      3. 5.1.3 Addressing Modes Summarized
    2. 5.2 Addressing Mode Fields
      1. 5.2.1 ADDR1 Field
      2. 5.2.2 ADDR2 Field
      3. 5.2.3 ADDR3 Field
      4. 5.2.4 DIRM Field
      5. 5.2.5 Additional Fields
    3. 5.3 Alignment and Pipeline Considerations
      1. 5.3.1 Alignment
      2. 5.3.2 Pipeline Considerations
    4. 5.4 Types of Addressing Modes
      1. 5.4.1 Direct Addressing
      2. 5.4.2 Pointer Addressing
        1. 5.4.2.1 Pointer Addressing with #Immediate Offset
        2. 5.4.2.2 Pointer Addressing with Pointer Offset
        3. 5.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 5.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 5.4.3 Stack Addressing
        1. 5.4.3.1 Allocating and De-allocating Stack Space
      4. 5.4.4 Circular Addressing Instruction
      5. 5.4.5 Bit Reversed Addressing Instruction
  8. 6Safety and Security Unit (SSU)
    1. 6.1 SSU Overview
    2. 6.2 Links and Task Isolation
    3. 6.3 Sharing Data Outside Task Isolation Boundary
    4. 6.4 Protected Call and Return
  9. 7Emulation
    1. 7.1 Overview of Emulation Features
    2. 7.2 Debug Terminology
    3. 7.3 Debug Interface
    4. 7.4 Execution Control Mode
    5. 7.5 Breakpoints, Watchpoints, and Counters
      1. 7.5.1 Software Breakpoint
      2. 7.5.2 Hardware Debugging Resources
        1. 7.5.2.1 Hardware Breakpoint
        2. 7.5.2.2 Hardware Watchpoint
        3. 7.5.2.3 Benchmark Counters
      3. 7.5.3 PC Trace
  10. 8Revision History

4.11 Protection During Interrupt

Table 4-11 is the pipeline diagram for Interrupt context save and restore. ML is last instruction of current execution that was interrupted, ML-U is the latest time when a register update can happen because of an ML instruction, context save must take the latest value. Once the registers are sampled for context save, the registers are cleared for security reasons, CLR indicates the cycle in which the registers are cleared. Context save (CS) takes 8 cycles, CS1 to CS8. ISR instructions are I1 to I6. Context save overlaps with these instructions; hence, RETI.RTINT can not be executed for 6 cycles as the Realtime stack can not be read until the context save is complete. I6-U is the last instruction of the ISR that can update registers. CR1 to CR8 are context restore cycles, MN is the first instruction after an ISR exit, this instruction must read register values that are restored from the Realtime stack. Register updates due to I6 must be complete before registers are restored. MN-RD is the earliest time a register can be read. Any overlap of these mentioned operations triggers a pipeline protection and the current operation is stalled until the conflict is resolved.

Table 4-11 Interrupt Pipeline Diagram
Cycle Pipeline Phase RTINT Stack Ax0-7 RETADDR
D2 R1 R2 R3 E1 E2 E3 E4 E5 E6 E7 E8
1
2
3
4 ML
5 CS1 ML
6 CS2 CS1 ML
7 CS3 CS2 CS1 ML
8 CS4 CS3 CS2 CS1 ML ML-U
9 CS5 CS4 CS3 CS2 CS1 ML
10 CS6 CS5 CS4 CS3 CS2 CS1 ML CLR
11 CS7 CS6 CS5 CS4 CS3 CS2 ML CS1-WR
12 CS8 CS7 CS6 CS5 CS4 CS3 ML CS2-WR
13 I1 CS8 CS7 CS6 CS5 CS4 ML CS3-WR I1-RW
14 I2 I1 CS8 CS7 CS6 CS5 ML CS4-WR
15 I3 I2 I1 CS8 CS7 CS6 CS5-WR
16 I4 I3 I2 I1 CS8 CS7 CS6-WR
17 I5 I4 I3 I2 I1 CS8 CS7-WR
18 I6 I5 I4 I3 I2 I1 CS8-WR
19 CR1 I6 I5 I4 I3 I2 I1 CR1-RD
20 CR2 I6 I5 I4 I3 I2 I1 CR2-RD
21 CR3 I6 I5 I4 I3 I2 I1 CR3-RD
22 CR4 I6 I5 I4 I3 I2 I1 CR4-RD CR1
23 CR5 I6 I5 I4 I3 I2 I1 CR5-RD I6-U
24 CR6 I6 I5 I4 I3 I2 CR6-RD
25 CR7 I6 I5 I4 I3 CR7-RD
26 CR8 I6 I5 I4 CR8-RD
27 MN I6 I5 MN-RD
28 MN I6
29 MN
30 MN
31 MN
32 MN