SPRUIY2 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
      3. 3.2.3 RTINT (Real Time Interrupt)
      4. 3.2.4 INT (Low-Priority Interrupt)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Pipeline
    1. 4.1  Introduction
    2. 4.2  Decoupled Pipeline Phases
    3. 4.3  Dual Instruction Prefetch Buffers
    4. 4.4  Pipeline Advancement and Stalls
    5. 4.5  Pipeline Hazards and Protection Mechanisms
    6. 4.6  Register Updates and Corresponding Pipeline Phases
    7. 4.7  Register Reads and Writes During Normal Operation
    8. 4.8  D2 Read Protection
    9. 4.9  E1 Read Protection
    10. 4.10 WAW Protection
    11. 4.11 Protection During Interrupt
  7. 5Addressing Modes
    1. 5.1 Addressing Modes Overview
      1. 5.1.1 Documentation and Implementation
      2. 5.1.2 List of Addressing Mode Types
        1. 5.1.2.1 Additional Types of Addressing
      3. 5.1.3 Addressing Modes Summarized
    2. 5.2 Addressing Mode Fields
      1. 5.2.1 ADDR1 Field
      2. 5.2.2 ADDR2 Field
      3. 5.2.3 ADDR3 Field
      4. 5.2.4 DIRM Field
      5. 5.2.5 Additional Fields
    3. 5.3 Alignment and Pipeline Considerations
      1. 5.3.1 Alignment
      2. 5.3.2 Pipeline Considerations
    4. 5.4 Types of Addressing Modes
      1. 5.4.1 Direct Addressing
      2. 5.4.2 Pointer Addressing
        1. 5.4.2.1 Pointer Addressing with #Immediate Offset
        2. 5.4.2.2 Pointer Addressing with Pointer Offset
        3. 5.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 5.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 5.4.3 Stack Addressing
        1. 5.4.3.1 Allocating and De-allocating Stack Space
      4. 5.4.4 Circular Addressing Instruction
      5. 5.4.5 Bit Reversed Addressing Instruction
  8. 6Safety and Security Unit (SSU)
    1. 6.1 SSU Overview
    2. 6.2 Links and Task Isolation
    3. 6.3 Sharing Data Outside Task Isolation Boundary
    4. 6.4 Protected Call and Return
  9. 7Emulation
    1. 7.1 Overview of Emulation Features
    2. 7.2 Debug Terminology
    3. 7.3 Debug Interface
    4. 7.4 Execution Control Mode
    5. 7.5 Breakpoints, Watchpoints, and Counters
      1. 7.5.1 Software Breakpoint
      2. 7.5.2 Hardware Debugging Resources
        1. 7.5.2.1 Hardware Breakpoint
        2. 7.5.2.2 Hardware Watchpoint
        3. 7.5.2.3 Benchmark Counters
      3. 7.5.3 PC Trace
  10. 8Revision History

7.3 Debug Interface

The target-level TI debug interface uses the five standard IEEE 1149.1 (JTAG) signals (TRST, TCK, TMS, TDI, and TDO) and the two TI extensions (EMU0 and EMU1). Figure 7-1 shows the 14-pin JTAG header that is used to interface the target to a scan controller, and Table 7-1 defines the pins. As listed in Table 7-1, the header requires more than the five JTAG signals and the TI extensions. The header also requires a test clock return signal (TCK_RET), the target supply (VCC), and ground (GND). TCK_RET is a test clock out of the scan controller and into the target system. The target system uses TCK_RET, if the target system does not supply a test clock (in which case TCK can not be used). In many target systems, TCK_RET is connected to TCK and used as the test clock.

F29x JTAG Header to Interface a Target to the Scan Controller Figure 7-1 JTAG Header to Interface a Target to the Scan Controller
Table 7-1 14-Pin Header Signal Descriptions
Signal Description Emulator State(1) Target State(1)
EMU0 Emulation pin 0 I I/O
EMU1 Emulation pin 1 I I/O
GND Ground
PD (VCC) Presence detect. Indicates that the emulation cable is connected and that the target is powered up. PD must be tied to VCC in the target system. I O
TCK Test clock. TCK is a clock source from the emulation cable pod. This signal can be used to drive the system test clock. O I
TCK_RET Test clock return. Test clock input to the emulator. Can be a buffered or unbuffered version of TCK. I O
TDI Test data input O I
TDO Test data output I O
TMS Test mode select O I
TRST(2) Test reset O I
(1) I = input; O = output
(2) Do not use pull-up resistors on TRST: an internal pull-down resistor is on the device. In a low-noise environment, TRST can be left floating. In a high-noise environment, an additional pull-down resistor can be needed. (The size of this resistor can be based on electrical current considerations.)

The state of the TRST, EMU0, and EMU1 signals at device power up determines the operating mode of the device. The operating mode takes effect as soon as the device has sufficient power to operate. If the TRST signal rises, the EMU0 and EMU1 signals are sampled on the rising edge and the operating mode is latched. Some of these modes are reserved for test purposes, but those that can be of use in a target system are detailed in Table 7-2. A target system is not required to support any mode other than normal mode.

Table 7-2 Selecting Device Operating Modes By Using TRST, EMU0, and EMU1
TRST EMU1 EMU0 Device Operating Mode JTAG Cable
Active?
Low Low Low Peripheral mode. Disables the CPU and memory portions of the C29x CPU. Another processor treats the C29x CPU as a peripheral. No
Low Low High Reserved for testing No
Low High Low Wait-in-reset mode. Prolongs the device’s reset until released by external means. This allows a C29x CPU to power up in reset, provided external hardware holds EMU0 low only while power-up reset is active. Yes
Low High High Normal mode with emulation disabled. This is the setting that must be used on target systems when a scan controller (such as the XDS510) is not attached. TRST is pulled down and EMU1 and EMU0 pulled up within the C29x CPU; this is the default mode. No
High Low or High Low or High Normal mode with emulation enabled. This is the setting to use on target systems when a scan controller is attached (the scan controller controls TRST). TRST must not be high during device power-up. Yes