SPRUIY2 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
      3. 3.2.3 RTINT (Real Time Interrupt)
      4. 3.2.4 INT (Low-Priority Interrupt)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Pipeline
    1. 4.1  Introduction
    2. 4.2  Decoupled Pipeline Phases
    3. 4.3  Dual Instruction Prefetch Buffers
    4. 4.4  Pipeline Advancement and Stalls
    5. 4.5  Pipeline Hazards and Protection Mechanisms
    6. 4.6  Register Updates and Corresponding Pipeline Phases
    7. 4.7  Register Reads and Writes During Normal Operation
    8. 4.8  D2 Read Protection
    9. 4.9  E1 Read Protection
    10. 4.10 WAW Protection
    11. 4.11 Protection During Interrupt
  7. 5Addressing Modes
    1. 5.1 Addressing Modes Overview
      1. 5.1.1 Documentation and Implementation
      2. 5.1.2 List of Addressing Mode Types
        1. 5.1.2.1 Additional Types of Addressing
      3. 5.1.3 Addressing Modes Summarized
    2. 5.2 Addressing Mode Fields
      1. 5.2.1 ADDR1 Field
      2. 5.2.2 ADDR2 Field
      3. 5.2.3 ADDR3 Field
      4. 5.2.4 DIRM Field
      5. 5.2.5 Additional Fields
    3. 5.3 Alignment and Pipeline Considerations
      1. 5.3.1 Alignment
      2. 5.3.2 Pipeline Considerations
    4. 5.4 Types of Addressing Modes
      1. 5.4.1 Direct Addressing
      2. 5.4.2 Pointer Addressing
        1. 5.4.2.1 Pointer Addressing with #Immediate Offset
        2. 5.4.2.2 Pointer Addressing with Pointer Offset
        3. 5.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 5.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 5.4.3 Stack Addressing
        1. 5.4.3.1 Allocating and De-allocating Stack Space
      4. 5.4.4 Circular Addressing Instruction
      5. 5.4.5 Bit Reversed Addressing Instruction
  8. 6Safety and Security Unit (SSU)
    1. 6.1 SSU Overview
    2. 6.2 Links and Task Isolation
    3. 6.3 Sharing Data Outside Task Isolation Boundary
    4. 6.4 Protected Call and Return
  9. 7Emulation
    1. 7.1 Overview of Emulation Features
    2. 7.2 Debug Terminology
    3. 7.3 Debug Interface
    4. 7.4 Execution Control Mode
    5. 7.5 Breakpoints, Watchpoints, and Counters
      1. 7.5.1 Software Breakpoint
      2. 7.5.2 Hardware Debugging Resources
        1. 7.5.2.1 Hardware Breakpoint
        2. 7.5.2.2 Hardware Watchpoint
        3. 7.5.2.3 Benchmark Counters
      3. 7.5.3 PC Trace
  10. 8Revision History

5.1.3 Addressing Modes Summarized

Table 5-1 summarizes all supported addressing modes and the various forms.

Table 5-1 Available Addressing Modes
Opcode Field Mnemonic Shorthand Address Generation
Direct Addressing
DIRM *(0:#u32imm) @u32imm addr = #u32imm
Pointer Addressing with #Immediate Offset: (Ax = A0 to A14 2, Az = A4 to A7)
DIRM *(Ax+#u28imm) *Ax[#u28imm] addr = Ax + #u28imm (#u28imm = 0 to 256MB range)
ADDR1 *(Ax+#u10imm) *Ax[#u10imm] addr = Ax + #u10imm (#u10imm = 0 to 1KB range)
ADDR1 *(Ax+#u10imm<<2) *Ax[#u10imm] addr = Ax + #u10imm<<2 (#u10imm << 2 = 0 to 4KB range, 4B steps)
ADDR3 *(Ax+#u8imm<<2) *Ax[#u8imm] addr = Ax + #u8imm<<2 (#u8imm << 2 = 0 to 1KB range, 4B steps)
ADDR2 *Az *Az addr = Az
Pointer Addressing with Pointer Offset: (Ax = A0 to A14 2, Aj = A0 to A14, Ak = A0 to A3, Az = A4 to A7)
ADDR1 *(Ax+Ak<<#u2imm) *Ax[Ak] addr = Ax + Ak << #u2imm (#u2imm = 0, 1, 2, 3)
ADDR1 *(Aj=(Ax+Ak<<#u2imm)) *Aj=Ax[Ak] addr = Ax + Ak << #u2imm, Aj = addr (#u2imm = 0, 1, 2, 3)
ADDR2 *(Az+A0<<#scale) *Az[A0] addr = Az + A0 << (0/1/2/3) 1
ADDR2 *(Az+A1<<#scale) *Az[A1] addr = Az + A1 << (0/1/2/3) 1
Pointer Addressing with #Immediate Increment/Decrement: (Ax = A0 to A14 2, Az = A4 to A7)
ADDR1 *(Ax++#u8imm) *Ax++[#u8imm] addr = Ax, Ax = Ax + #u8imm (#u8imm = 0 to 255 range)
ADDR1 *(Ax--#n8imm) *Ax--[#n8imm] addr = Ax, Ax = Ax - #n8imm (#n8imm = 1 to 256 range)
ADDR1 *(Ax-=#n8imm) *Ax-=[#n8imm] Ax = Ax - #n8imm, addr = Ax (#n8imm = 1 to 256 range)
ADDR2 *(Az++#size) *Az++ addr = Az, Az = Az + (1/2/4/8) (#size = 1,2,4,8) 1
ADDR2 *(Az--#size) *Az-- addr = Az, Az = Az – (1/2/4/8) (#size = 1,2,4,8) 1
ADDR2 *(Az-=#size) *--Az Az = Az – (1/2/4/8), addr = Az (#size = 1,2,4,8) 1
Pointer Addressing with Pointer Increment/Decrement: (Ax = A0 to A14 2, Ak = A0 to A3, Az = A4 to A7)
ADDR1 *(Ax+#u7imm)++Ak *Ax[#u7imm]++Ak addr = Ax + #u7imm, Ax = Ax + Ak (#u7imm = 0 to 128)
ADDR2 *(Az++A0) *Az++A0 addr = Az, Az = Az + A0
ADDR2 *(Az++A1) *Az++A1 addr = Az, Az = Az + A1
Stack Addressing: (A15 = SP)
ADDR1 *(A15-#n13imm) *A15-[#n13imm] addr = A15 - #n13imm (#n13imm = 1 to 8192)
ADDR1 *(A15++#u8imm) *A15++[#u8imm] addr = A15, A15 = A15 + #u8imm (#u8imm = 0 to 255)
ADDR1 *(A15-=#n8imm) *A15-=[#n8imm] A15 = A15 - #n8imm, addr = A15 (#n8imm = 1 to 256)
(1) The ADDR2 opcode field modes do not specify the increment step size ("#size") or scale amount ("#scale"). This is automatically performed by the CPU hardware based on the word size being accessed by the instruction. See Section 5.2 for more details.
(2) The Ax[0-14] addressing field can support the A15 register, however this is the stack pointer (SP) register and for some of the addressing modes, the operation is not valid for the SP and hence the addressing mode can not be used