SPRUIY2 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
      3. 3.2.3 RTINT (Real Time Interrupt)
      4. 3.2.4 INT (Low-Priority Interrupt)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Pipeline
    1. 4.1  Introduction
    2. 4.2  Decoupled Pipeline Phases
    3. 4.3  Dual Instruction Prefetch Buffers
    4. 4.4  Pipeline Advancement and Stalls
    5. 4.5  Pipeline Hazards and Protection Mechanisms
    6. 4.6  Register Updates and Corresponding Pipeline Phases
    7. 4.7  Register Reads and Writes During Normal Operation
    8. 4.8  D2 Read Protection
    9. 4.9  E1 Read Protection
    10. 4.10 WAW Protection
    11. 4.11 Protection During Interrupt
  7. 5Addressing Modes
    1. 5.1 Addressing Modes Overview
      1. 5.1.1 Documentation and Implementation
      2. 5.1.2 List of Addressing Mode Types
        1. 5.1.2.1 Additional Types of Addressing
      3. 5.1.3 Addressing Modes Summarized
    2. 5.2 Addressing Mode Fields
      1. 5.2.1 ADDR1 Field
      2. 5.2.2 ADDR2 Field
      3. 5.2.3 ADDR3 Field
      4. 5.2.4 DIRM Field
      5. 5.2.5 Additional Fields
    3. 5.3 Alignment and Pipeline Considerations
      1. 5.3.1 Alignment
      2. 5.3.2 Pipeline Considerations
    4. 5.4 Types of Addressing Modes
      1. 5.4.1 Direct Addressing
      2. 5.4.2 Pointer Addressing
        1. 5.4.2.1 Pointer Addressing with #Immediate Offset
        2. 5.4.2.2 Pointer Addressing with Pointer Offset
        3. 5.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 5.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 5.4.3 Stack Addressing
        1. 5.4.3.1 Allocating and De-allocating Stack Space
      4. 5.4.4 Circular Addressing Instruction
      5. 5.4.5 Bit Reversed Addressing Instruction
  8. 6Safety and Security Unit (SSU)
    1. 6.1 SSU Overview
    2. 6.2 Links and Task Isolation
    3. 6.3 Sharing Data Outside Task Isolation Boundary
    4. 6.4 Protected Call and Return
  9. 7Emulation
    1. 7.1 Overview of Emulation Features
    2. 7.2 Debug Terminology
    3. 7.3 Debug Interface
    4. 7.4 Execution Control Mode
    5. 7.5 Breakpoints, Watchpoints, and Counters
      1. 7.5.1 Software Breakpoint
      2. 7.5.2 Hardware Debugging Resources
        1. 7.5.2.1 Hardware Breakpoint
        2. 7.5.2.2 Hardware Watchpoint
        3. 7.5.2.3 Benchmark Counters
      3. 7.5.3 PC Trace
  10. 8Revision History

4.5 Pipeline Hazards and Protection Mechanisms

The C29x CPU instructions operate by utilizing and updating registers in different stages of the pipeline, while memory reads and writes occur in separate stages of the pipeline. One of the effects of having operations for an instruction in different phases of the pipeline is that pipeline conflicts (also known as pipeline hazards) are possible. There are three main types of hazards in any pipelined architecture.

  1. Control Hazard: A control hazard occurs due to discontinuities in the execution sequence. The D2 controller and Instruction buffer control mechanism are responsible for automatically handling such hazards, there is a possibility discarding some instruction packets. To minimize cycle overhead, the user assembly code can choose to have discontinuity instructions (except CALL.PROT, RET.PROT and LB.PROT ) execute instructions in the delay slots of a discontinuity. This decision is part of the opcode of the discontinuity instruction.
  2. Structural Hazard: The C29x CPU does not present any structural hazards for instruction execution. However, there is a structural hazard that can occur in the context-save and restore sequence when handling Realtime Interrupts or Non-Maskable Interrupts (NMIs). This hazard occurs due to the timing of the pipeline operations during the interrupt context save and restore process. For the RETI.RTINT instruction to restore the CPU register contents, RETI.RTINT instruction must be preceded by a minimum of 6 instruction packets. If the RETI.RTINT instruction is executed less than 6 instruction packets after the interrupt service routine is entered, hardware pipeline protection gets activated.
  3. Data Hazard: Almost all the hazards in the C29x CPU pipeline fall into the category of data hazards. These hazards can arise from different scenarios, such as a write operation to a memory location before a read operation from the same memory location, or a write operation to a register before a read operation from the same register. The C29x CPU pipeline controller has hardware to detect these data hazards and generate pipeline protection stall cycles to make sure that the instruction execution sequence is not affected.
  4. WAW Hazard: A Write-after-Write (WAW) hazard occurs when a resource (like a register) can be updated in multiple phases of the pipeline.
    • Instructions that update Ax registers during the D2 phase of the pipeline can cause WAW hazards due to the fact that Ax registers can now be loaded from memory or Mx registers moved in the E1 phase of the pipeline. This allows for a sequence of instructions to update the same Ax register out of order or in the same cycle.
    • In the E1 phase, operations that update the Dx and Mx registers are composed of both single cycle and multicycle instructions. This means that some instructions can update the Dx/Mx register after the E1 phase is complete, while others take several cycles (E2 - E6) to update the Dx/Mx register. As a result, a sequence of instructions can cause a WAW hazard by updating the same Dx/Mx register either out of order or in the same cycle.

Lets look into the data hazard example shown in Table 4-2 and Figure 4-3.

Table 4-2 Sample Instruction Sequence with Data Hazard
Instruction Packet Label for Reference Comments
MV D8, #0x1231156 IPKT-1
MV M6, #0x4022F983 IPKT-2
MV D2, #0x2 IPKT-3
FTOS16 D7, M6 IPKT-4
LD.32 A4, *A0 IPKT-5 A4 register is loaded at the end of E1 phase of the instruction.
CMP D7, D8 IPKT-6
ADD.U16 A4, A4, #0x20 IPKT-7 ADD of A4 register happens in the D2 phase of the pipeline. This instruction uses A4 register that was loaded in IPKT-5.
MV D4, #0x5 IPKT-8

In the absence of hardware pipeline protection, when the above instruction packet sequence is executed, the load of the A4 register by IPKT-5 occur in the W phase of the pipeline, while the add operation of IPKT-7 (D2 phase of the pipeline) takes place earlier in the same cycle and thus use the old value of the A4 register. The C29x CPU has hardware pipeline protection mechanisms that makes sure any resource used as a source operand in an instruction is only utilized after any pending updates by any previous instructions are finished. If the source operand is a memory location, then any pending writes to the same address (or address block for certain regions that are block protected) by previous instructions are issued before the read. The hardware pipeline protection mechanism detects that IPKT-7 is using the A4 register before A4 is updated by IPKT-5, and inserts stall cycles so that IPKT-7 is held in the D2 phase until the A4 register update is completed. This is shown in Figure 4-3.

F29x Pipeline Diagram Depicting D2 Stall Due to Pipeline Protection Figure 4-3 Pipeline Diagram Depicting D2 Stall Due to Pipeline Protection