SPRUIY2 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation from Texas Instruments
    3.     Glossary
    4.     Support Resources
    5.     Trademarks
  3. 1Architecture Overview
    1. 1.1 Introduction to the CPU
    2. 1.2 Data Type
    3. 1.3 C29x CPU System Architecture
      1. 1.3.1 Emulation Logic
      2. 1.3.2 CPU Interface Buses
    4. 1.4 Memory Map
  4. 2Central Processing Unit (CPU)
    1. 2.1 C29x CPU Architecture
      1. 2.1.1 Features
      2. 2.1.2 Block Diagram
    2. 2.2 CPU Registers
      1. 2.2.1 Addressing Registers (Ax/XAx)
      2. 2.2.2 Fixed-Point Registers (Dx/XDx)
      3. 2.2.3 Floating Point Register (Mx/XMx)
      4. 2.2.4 Program Counter (PC)
      5. 2.2.5 Return Program Counter (RPC)
      6. 2.2.6 Status Registers
        1. 2.2.6.1 Interrupt Status Register (ISTS)
        2. 2.2.6.2 Decode Phase Status Register (DSTS)
        3. 2.2.6.3 Execute Phase Status Register (ESTS)
    3. 2.3 Instruction Packing
      1. 2.3.1 Standalone Instructions and Restrictions
      2. 2.3.2 Instruction Timeout
    4. 2.4 Stacks
      1. 2.4.1 Software Stack
      2. 2.4.2 Protected Call Stack
      3. 2.4.3 Real Time Interrupt / NMI Stack
  5. 3Interrupts
    1. 3.1 CPU Interrupts Architecture Block Diagram
    2. 3.2 RESET, NMI, RTINT, and INT
      1. 3.2.1 RESET (CPU reset)
      2. 3.2.2 NMI (Non-Maskable Interrupt)
      3. 3.2.3 RTINT (Real Time Interrupt)
      4. 3.2.4 INT (Low-Priority Interrupt)
    3. 3.3 Conditions Blocking Interrupts
      1. 3.3.1 ATOMIC Counter
    4. 3.4 CPU Interrupt Control Registers
      1. 3.4.1 Interrupt Status Register (ISTS)
      2. 3.4.2 Decode Phase Status Register (DSTS)
      3. 3.4.3 Interrupt-Related Stack Registers
    5. 3.5 Interrupt Nesting
      1. 3.5.1 Interrupt Nesting Example Diagram
    6. 3.6 Security
      1. 3.6.1 Overview
      2. 3.6.2 LINK
      3. 3.6.3 STACK
      4. 3.6.4 ZONE
  6. 4Pipeline
    1. 4.1  Introduction
    2. 4.2  Decoupled Pipeline Phases
    3. 4.3  Dual Instruction Prefetch Buffers
    4. 4.4  Pipeline Advancement and Stalls
    5. 4.5  Pipeline Hazards and Protection Mechanisms
    6. 4.6  Register Updates and Corresponding Pipeline Phases
    7. 4.7  Register Reads and Writes During Normal Operation
    8. 4.8  D2 Read Protection
    9. 4.9  E1 Read Protection
    10. 4.10 WAW Protection
    11. 4.11 Protection During Interrupt
  7. 5Addressing Modes
    1. 5.1 Addressing Modes Overview
      1. 5.1.1 Documentation and Implementation
      2. 5.1.2 List of Addressing Mode Types
        1. 5.1.2.1 Additional Types of Addressing
      3. 5.1.3 Addressing Modes Summarized
    2. 5.2 Addressing Mode Fields
      1. 5.2.1 ADDR1 Field
      2. 5.2.2 ADDR2 Field
      3. 5.2.3 ADDR3 Field
      4. 5.2.4 DIRM Field
      5. 5.2.5 Additional Fields
    3. 5.3 Alignment and Pipeline Considerations
      1. 5.3.1 Alignment
      2. 5.3.2 Pipeline Considerations
    4. 5.4 Types of Addressing Modes
      1. 5.4.1 Direct Addressing
      2. 5.4.2 Pointer Addressing
        1. 5.4.2.1 Pointer Addressing with #Immediate Offset
        2. 5.4.2.2 Pointer Addressing with Pointer Offset
        3. 5.4.2.3 Pointer Addressing with #Immediate Increment/Decrement
        4. 5.4.2.4 Pointer Addressing with Pointer Increment/Decrement
      3. 5.4.3 Stack Addressing
        1. 5.4.3.1 Allocating and De-allocating Stack Space
      4. 5.4.4 Circular Addressing Instruction
      5. 5.4.5 Bit Reversed Addressing Instruction
  8. 6Safety and Security Unit (SSU)
    1. 6.1 SSU Overview
    2. 6.2 Links and Task Isolation
    3. 6.3 Sharing Data Outside Task Isolation Boundary
    4. 6.4 Protected Call and Return
  9. 7Emulation
    1. 7.1 Overview of Emulation Features
    2. 7.2 Debug Terminology
    3. 7.3 Debug Interface
    4. 7.4 Execution Control Mode
    5. 7.5 Breakpoints, Watchpoints, and Counters
      1. 7.5.1 Software Breakpoint
      2. 7.5.2 Hardware Debugging Resources
        1. 7.5.2.1 Hardware Breakpoint
        2. 7.5.2.2 Hardware Watchpoint
        3. 7.5.2.3 Benchmark Counters
      3. 7.5.3 PC Trace
  10. 8Revision History

5.4.5 Bit Reversed Addressing Instruction

The C29x CPU does not support a native bit reversed addressing mode like on the C28x CPU. However, the functional parallelism present in the C29x CPU architecture makes sure that there is no performance impact for the lack of native bit reversed addressing mode.

Bit reversed addressing is performed by an instruction that modifies the addressing registers in a bit reversed fashion and is typically used for re-ordering data for Fast-Fourier Transform (FFT) type algorithms.

Table 5-8 Bit Reversed Addressing Visualized
Address Value Bit Reversed Address Bit Reversed Value
0000 0 0000 0
0001 1 1000 8
0010 2 0100 4
0011 3 1100 12
0100 4 0010 2
0101 5 1010 10
0110 6 0110 6
0111 7 1110 14
1000 8 0001 1
1001 9 1001 9
1010 10 0101 5
... ... ... ...

The supported instruction for bit reversed addressing is:

ADD.BITREV Az,Ay,Ax

Perform the ADD operation, but add the bits from left to right (unlike a standard ADD that is from right to left). An example is:

; Ax = 0011 1001
; Ay = 0000 1000
; Az = 0011 0101 (after a bit reversed add):
ADD          Az,Ay,Ax    ; Normal Add:        Az = 0100 0001
ADD.BITREV   Az,Ay,Ax    ; Bit Reversed Add:  Az = 0011 0101

The following example shows how this operation is used to reverse an array of Data in bit reversed order:

BitReversedIndex        = 0;
BitReversedIncrement    = N/2;
for(i=0; i < N; i++)
{
    BitReversedDataArray[BitReversedIndex] = NormalDataArray[i];
    BitReversedIndex = BitReversedAdd(BitReversedIndex+BitReversedIncrement);
}

Typically, when bit reversing data, the data array is a multiple of 2 in size (N = 16, 32, 64, 128, and so on).

The BitReversedIncrement then needs to be set to half the array size (N/2) to increment by 1 in bit reversed order.

The assembly code for the previous operation is:

MV              A0,#0                       ; A0 = BitReversedIndex = 0
MV              A8,#N/2                     ; A8 = Increment Step = N/2
MV              A4,#NormalDataArray         ; A4 = Stating Address Of 
                                            ;      NormalDataArray
MV              A5,#BitReversedDataArray    ; A5 = Stating Address Of 
                                            ;      BitReversedDataArray

; Repeat N times:
LD.32           D0,*A4++                    ; Read From NormalDataArray
ST.32           *(A5+A0),D0                 ; Write To BitReversedDataArray    
||ADD.BITREV    A0,A0,A8                    ; Increment BitReversedIndex
LD.32           D0,*A4++                    ; Read From NormalDataArray
ST.32           *(A5+A0),D0                 ; Write To BitReversedDataArray    
||ADD.BITREV    A0,A0,A8                    ; Increment BitReversedIndex
....
LD.32           D0,*A4++                    ; Read From NormalDataArray
ST.32           *(A5+A0),D0                 ; Write To BitReversedDataArray    
||ADD.BITREV    A0,A0,A8                    ; Increment BitReversedIndex