SPRUIY3 February   2023 TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Feature Differences Between F28002x, F280015x and F280013x
    1. 1.1 F28002x, F280015x and F280013x Feature Comparison
      1. 1.1.1 F28002x, F280013x and F280015x Superset Device Comparison
  4. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 80-Pin PN, 64-Pin PM and 48-Pin PT or PHP Packages
    2. 2.2 New and Existing PCB Migration
  5. 3Feature Differences for System Consideration
    1. 3.1 New Features in F280013x and F280015x
      1. 3.1.1 Secure Boot/JTAG Lock
      2. 3.1.2 Embedded Pattern Generator (EPG)
      3. 3.1.3 Lockstep Compare Module (LCM)
      4. 3.1.4 INTOSC External Precision Resistor (ExtR)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
      1. 3.4.1 CMPSS Module Variants
    5. 3.5 Other Device Changes
      1. 3.5.1 PIE Channel Mapping
      2. 3.5.2 Bootrom
      3. 3.5.3 CLB and Motor Control Libraries
      4. 3.5.4 AGPIO
        1. 3.5.4.1 AGPIO Filter
        2. 3.5.4.2 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  6. 4Application Code Migration From F28002x to F280015x or F280013x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  7. 5Specific Use Cases Related to F280015x and F280013x New Features
    1. 5.1 EPG
  8. 6EABI Support
    1. 6.1 Flash API
  9. 7References

3.5.4.2 Digital Inputs and Outputs on ADC Pins (AGPIOs)

Some GPIOs on this device are multiplexed with analog pins. These are also referred to as AGPIOs. Unlike AIOs, AGPIOs have full input and output capability.

By default the AGPIOs are not connected and have to be configured. Table 3-9 shows how to configure the AGPIOs.

Table 3-9 AGPIO Configuration
AGPIOCTRLA.GPIOy
(Default = 0)		 GPAxMSEL.GPIOy
(Default = 1)		 Pin Connected To:
ADC GPIOy
0 0 - Yes
0 1 -(1) -(1)
1 0 - Yes
1 1 Yes -
(1) By default there are no signals connected to AGPIO pins. One of the other rows in the table must be chosen for pin functionality.
Note: If digital signals with sharp edges (high dv/dt) are connected to the AGPIOs, cross-talk can occur with adjacent analog signals. The user should therefore limit the edge rate of signals connected to AGPIOs if adjacent channels are being used for analog functions.