SPRUIY4B February 2023 – May 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1
The following critical LCM registers are protected by a parity scheme:
The parity scheme provides one parity bit per byte of data in the corresponding registers. Updates to any of the constantly-monitored registers causes an update to the parity bit. A single bit fault can therefore immediately flag an error. If the parity check determines a parity error has occurred, a dedicated error output line from the LCM module flags an error to the system.
All register parity errors (from the LCM) are combined into a single NMI to the NMIWD module as REGPARITYERR. The status of the register parity error specific to the LCM can also be viewed in the SYS_STATUS_REGS[REGPARITY_ERR_FLG.LCMx] bits.
Upon a parity error detection, SYSRSN must be asserted and the LCM_REGS[LCM_STATUS_CLEAR] register must then be cleared using the a write of 1 to all appropriate bits in the register.
Details on the self-test capability of the register parity error test are explained in Section 3.8.3.