SPRUIY4B February 2023 – May 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1
Table 4-200 lists the memory-mapped registers for the SYS_STATUS_REGS registers. All register offset addresses not listed in Table 4-200 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
10h | SYS_ERR_INT_FLG | Status of interrupts due to multiple different errors in the system. | Go | |
12h | SYS_ERR_INT_CLR | SYS_ERR_INT_FLG clear register | Go | |
14h | SYS_ERR_INT_SET | SYS_ERR_INT_FLG set register | EALLOW | Go |
16h | SYS_ERR_MASK | SYS_ERR_MASK register | EALLOW | Go |
18h | LCM_ERR_FLG | Status register indicating lockstep compare error flag | Go | |
1Ah | LCM_ERR_FLG_CLR | LCM_ERR_FLG clear register | Go | |
1Ch | LCM_ERR_FLG_SET | LCM_ERR_FLG set register | EALLOW | Go |
20h | REGPARITY_ERR_FLG | Status register indicating register parity error flag | Go | |
22h | REGPARITY_ERR_FLG_CLR | REGPARITY_ERR_FLG clear register | Go | |
24h | REGPARITY_ERR_FLG_SET | REGPARITY_ERR_FLG set register | EALLOW | Go |
26h | REGPARITY_ERR_FLG_MASK | REGPARITY_ERR_FLG mask register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 4-201 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
SYS_ERR_INT_FLG is shown in Figure 4-178 and described in Table 4-202.
Return to the Summary Table.
Status of interrupts due to multiple different errors in the system.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | FPU_OFLOW | FPU_UFLOW | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPG1_INT | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RAM_ACC_VIOL | RESERVED | CORRECTABLE_ERR | RESERVED | GINT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19 | RESERVED | R | 0h | Reserved |
18 | RESERVED | R | 0h | Reserved |
17 | FPU_OFLOW | R | 0h | 0: FPU_OFLOW has not fired an interrupt. 1: FPU_OFLOW has fired an interrupt Reset type: SYSRSn |
16 | FPU_UFLOW | R | 0h | 0: FPU_UFLOW has not fired an interrupt. 1: FPU_UFLOW has fired an interrupt Reset type: SYSRSn |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | RESERVED | R | 0h | Reserved |
11 | EPG1_INT | R | 0h | 0: EPG1_INT has not fired an interrupt. 1: EPG1_INT has fired an interrupt Reset type: SYSRSn |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RAM_ACC_VIOL | R | 0h | 0: None of the Masters have violated the set protection rules 1: At least one of the master accesses has violated one or more of the access protection rules Reset type: SYSRSn |
3 | RESERVED | R | 0h | Reserved |
2 | CORRECTABLE_ERR | R | 0h | 0: Number of correctable errors detected has not exceeded the set threshold for flash/RAM. 1:Number of correctable errors detected has exceeded the set threshold for flash/RAM. Reset type: SYSRSn |
1 | RESERVED | R | 0h | Reserved |
0 | GINT | R | 0h | Global Interrupt flag: 0: On any of the flags of SYS_ERR_INT_FLG register being set, SYS_ERR_INT is pulsed and GINT flag would be set 1: No further interrupts would be fired until GINT flag is cleared Reset type: SYSRSn |
SYS_ERR_INT_CLR is shown in Figure 4-179 and described in Table 4-203.
Return to the Summary Table.
SYS_ERR_INT_FLG clear register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | FPU_OFLOW | FPU_UFLOW | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPG1_INT | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RAM_ACC_VIOL | RESERVED | CORRECTABLE_ERR | RESERVED | GINT |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19 | RESERVED | R-0/W1S | 0h | Reserved |
18 | RESERVED | R-0/W1S | 0h | Reserved |
17 | FPU_OFLOW | R-0/W1S | 0h | 0: No effect 1: FPU_OFLOW flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
16 | FPU_UFLOW | R-0/W1S | 0h | 0: No effect 1: FPU_UFLOW flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
15 | RESERVED | R-0/W1S | 0h | Reserved |
14 | RESERVED | R-0/W1S | 0h | Reserved |
13 | RESERVED | R-0/W1S | 0h | Reserved |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | EPG1_INT | R-0/W1S | 0h | 0: No effect 1: EPG1_INT flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RAM_ACC_VIOL | R-0/W1S | 0h | 0: No effect 1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | CORRECTABLE_ERR | R-0/W1S | 0h | 0: No effect 1: CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
1 | RESERVED | R-0/W1S | 0h | Reserved |
0 | GINT | R-0/W1S | 0h | 0: No effect 1: GINT flag of SYS_ERR_INT_FLG reister will be cleared. Reset type: SYSRSn |
SYS_ERR_INT_SET is shown in Figure 4-180 and described in Table 4-204.
Return to the Summary Table.
SYS_ERR_INT_FLG set register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | FPU_OFLOW | FPU_UFLOW | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPG1_INT | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RAM_ACC_VIOL | RESERVED | CORRECTABLE_ERR | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | R-0/W | 0h | A value of 0xa5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: SYSRSn |
23-20 | RESERVED | R | 0h | Reserved |
19 | RESERVED | R-0/W1S | 0h | Reserved |
18 | RESERVED | R-0/W1S | 0h | Reserved |
17 | FPU_OFLOW | R-0/W1S | 0h | 0: No effect 1: FPU_OFLOW flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
16 | FPU_UFLOW | R-0/W1S | 0h | 0: No effect 1: FPU_UFLOW flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
15 | RESERVED | R-0/W1S | 0h | Reserved |
14 | RESERVED | R-0/W1S | 0h | Reserved |
13 | RESERVED | R-0/W1S | 0h | Reserved |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | EPG1_INT | R-0/W1S | 0h | 0: No effect 1: EPG1_INT flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RAM_ACC_VIOL | R-0/W1S | 0h | 0: No effect 1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | CORRECTABLE_ERR | R-0/W1S | 0h | 0: No effect 1: CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be set. Reset type: SYSRSn |
1 | RESERVED | R-0/W1S | 0h | Reserved |
0 | RESERVED | R | 0h | Reserved |
SYS_ERR_MASK is shown in Figure 4-181 and described in Table 4-205.
Return to the Summary Table.
SYS_ERR_MASK register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | FPU_OFLOW | FPU_UFLOW | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPG1_INT | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RAM_ACC_VIOL | RESERVED | CORRECTABLE_ERR | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | R/W | 0h | A value of 0xa5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: SYSRSn |
23-20 | RESERVED | R | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | FPU_OFLOW | R/W | 0h | 0: FPU_OFLOW flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: FPU_OFLOW flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
16 | FPU_UFLOW | R/W | 0h | 0: FPU_UFLOW flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: FPU_UFLOW flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | EPG1_INT | R/W | 0h | 0: EPG1_INT flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: EPG1_INT flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RAM_ACC_VIOL | R/W | 0h | 0: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: RAM_ACC_VIOL flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | CORRECTABLE_ERR | R/W | 0h | 0: CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will be set on a hardware event. 1: CORRECTABLE_ERR flag of SYS_ERR_INT_FLG reister will not be set on a hardware event. Reset type: SYSRSn |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R | 0h | Reserved |
LCM_ERR_FLG is shown in Figure 4-182 and described in Table 4-206.
Return to the Summary Table.
Status register indicating lockstep compare error flag
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU | GERR | |||||
R-0-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | CPU | R | 0h | 0: CPU1 Lockstep compare error has not occurred. 1: CPU1 Lockstep compare error has occured. Reset type: PORESETn |
0 | GERR | R | 0h | Global Error event flag: 0: On any of the flags of LCM_ERR_FLG register being set, LCM_ERR_NMI is pulsed and GERR flag would be set 1: No further NMIs would be fired until GERR flag is cleared Reset type: PORESETn |
LCM_ERR_FLG_CLR is shown in Figure 4-183 and described in Table 4-207.
Return to the Summary Table.
LCM_ERR_FLG clear register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0/W1S-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0/W1S-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0/W1S-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU | GERR | |||||
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | CPU | R-0/W1S | 0h | 0: No effect 1: CPU flag of LCM_ERR_FLG reister will be cleared. Reset type: PORESETn |
0 | GERR | R-0/W1S | 0h | 0: No effect 1: GERR flag of LCM_ERR_FLG reister will be cleared. Reset type: PORESETn |
LCM_ERR_FLG_SET is shown in Figure 4-184 and described in Table 4-208.
Return to the Summary Table.
LCM_ERR_FLG set register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU | RESERVED | |||||
R-0-0h | R-0/W1S-0h | R-0-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | R-0/W | 0h | A value of 0xa5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: PORESETn |
23-2 | RESERVED | R-0 | 0h | Reserved |
1 | CPU | R-0/W1S | 0h | 0: No effect 1: CPU flag of LCM_ERR_FLG reister will be set Reset type: PORESETn |
0 | RESERVED | R-0 | 0h | Reserved |
REGPARITY_ERR_FLG is shown in Figure 4-185 and described in Table 4-209.
Return to the Summary Table.
Status register indicating register parity error flag
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU | GERR | |||||
R-0-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | CPU | R | 0h | 0: Register parity error is not generated from the lockstep compare module 1: Register parity error is generated from the lockstep compare module Reset type: PORESETn |
0 | GERR | R | 0h | Global Error event flag: 0: On any of the flags of REGPARITY_ERR_FLG register being set, REGPARITY_ERR_NMI is pulsed and GERR flag would be set 1: No further NMIs would be fired until GERR flag is cleared Reset type: PORESETn |
REGPARITY_ERR_FLG_CLR is shown in Figure 4-186 and described in Table 4-210.
Return to the Summary Table.
REGPARITY_ERR_FLG clear register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU | GERR | |||||
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | CPU | R-0/W1S | 0h | 0: No effect 1: CPU flag of REGPARITY_ERR_FLG reister will be cleared. Reset type: PORESETn |
0 | GERR | R-0/W1S | 0h | 0: No effect 1: GERR flag of REGPARITY_ERR_FLG reister will be cleared. Reset type: PORESETn |
REGPARITY_ERR_FLG_SET is shown in Figure 4-187 and described in Table 4-211.
Return to the Summary Table.
LCM_ERR_FLG set register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU | RESERVED | |||||
R-0-0h | R-0/W1S-0h | R-0-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | R-0/W | 0h | A value of 0xa5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: PORESETn |
23-2 | RESERVED | R-0 | 0h | Reserved |
1 | CPU | R-0/W1S | 0h | 0: No effect 1: CPU flag of REGPARITY_ERR_FLG reister will be set Reset type: PORESETn |
0 | RESERVED | R-0 | 0h | Reserved |
REGPARITY_ERR_FLG_MASK is shown in Figure 4-188 and described in Table 4-212.
Return to the Summary Table.
LCM_ERR_FLG mask register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU | RESERVED | |||||
R-0-0h | R/W-0h | R-0-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | KEY | R-0/W | 0h | A value of 0xa5 to this field would enable write to the other bit fields of this register. Any other value written to KEY field would block the write to the other fields of this register. Note: Only a 32 bit write to this register will succeed in updating the fields of this rigister, provided the correct value written to the KEY field simultaneously Reset type: PORESETn |
23-2 | RESERVED | R-0 | 0h | Reserved |
1 | CPU | R/W | 0h | 0: CPU flag of REGPARITY_ERR_FLG reister will be set on a hardware event. 1: CPU flag of REGPARITY_ERR_FLG reister will not be set on a hardware event. Reset type: PORESETn |
0 | RESERVED | R-0 | 0h | Reserved |