SPRUIY4B February 2023 – May 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1
The boot ROM code involves several memory addresses and registers used during execution. There are two sets of configurations; one for emulation and one for standalone boot flow. The emulation locations located in RAM emulate the OTP configurations and can be written to as many times as needed. The user configurable DCSM OTP locations used in the standalone boot flow program the device OTP and hence can only be written once. Table 5-14 details these locations. For bit field configuration details for BOOTPIN-CONFIG and BOOTDEF, see Section 5.4.1 and Section 5.4.2.
Additionally, the boot ROM supports boot configurations from DCSM zone 1 and zone 2 registers. Zone 2 configurations supercede zone 1 configurations, so it is recommended to use zone 1 configurations and use zone 2 as a secondary option.
Boot Flow | Register Name | Boot ROM Name | Register Address | User OTP Address |
---|---|---|---|---|
Emulation | - | EMU-BOOTPIN-CONFIG | 0x0000 0D00 | - |
- | EMU-GPREG2 | 0x0000 0D02 | - | |
- | EMU-BOOTDEF-LOW | 0x0000 0D04 | - | |
- | EMU-BOOTDEF-HIGH | 0x0000 0D06 | - | |
Standalone (Using Z1) |
Z1-GPREG1 | Z1-OTP-BOOTPIN-CONFIG | 0x0005 F008 | 0x0007 8008 |
Z1-GPREG2 | Z1-OTP-BOOT-GPREG2 | 0x0005 F00A | 0x0007 800A | |
Z1-GPREG3 | Z1-OTP-BOOTDEF-LOW | 0x0005 F00C | 0x0007 800C | |
Z1-GPREG4 | Z1-OTP-BOOTDEF-HIGH | 0x0005 F00E | 0x0007 800E | |
Standalone (Using Z2) |
Z2-GPREG1 | Z2-OTP-BOOTPIN-CONFIG | 0x0005 F088 | 0x0007 8208 |
Z2-GPREG2 | Z2-OTP-BOOT-GPREG2 | 0x0005 F08A | 0x0007 820A | |
Z2-GPREG3 | Z2-OTP-BOOTDEF-LOW | 0x0005 F08C | 0x0007 820C | |
Z2-GPREG4 | Z2-OTP-BOOTDEF-HIGH | 0x0005 F08E | 0x0007 820E |