SPRUIY4B February 2023 – May 2024 TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1
Data consistency is provided by indirect accesses to the message objects. During normal operation, all CPU accesses to the message RAM are done through Interface registers. The IFx registers can be thought of as a "window" through which the message objects (mailboxes) are accessed.
Three Interface register sets control the CPU read and write accesses to the Message RAM, see Figure 17-2. There are two Interface register sets for read/write access (IF1 and IF2) and one Interface register set for read access only (IF3). See also Section 17.12. The Interface registers have the same word length as the message RAM.
In a dedicated test mode, the message RAM is memory-mapped and can be directly accessed.