SPRUJ07 august   2023 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F2837x and F28P65x
    1. 1.1 F2837x and F28P65x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 176-Pin PTP and 100-Pin PZP Package
    2. 2.2 Use of Existing 176-Pin F2837x PCB Design
      1.      9
      2. 2.2.1 JTAG TRSTn No-Connect
      3. 2.2.2 GPIO Input Buffer Control Register
      4. 2.2.3 176-Pin GPIO Pin/Multiplex and ADCD Considerations
        1. 2.2.3.1 176-Pin PTP Pins with Different GPIO Assignment
        2. 2.2.3.2 ADCD Channel Migration
    3. 2.3 176-Pin PTP New PCB Design
    4. 2.4 100-Pin PZP New PCB Design
    5. 2.5 337-BGA ZWT Application to 256-BGA ZEJ or 169-BGA NMR
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P65x
      1. 3.1.1 Lock-step Compare Module (LCM)
      2. 3.1.2 Expanded Analog Channels
      3. 3.1.3 Firmware Update (FWU)
      4. 3.1.4 Flexible GPIO and Digital Input Pins
      5. 3.1.5 ADC Hardware Redundancy Safety Checker
      6. 3.1.6 Flexible Memory Sharing between CPU Subsystems
      7. 3.1.7 Increased RAM Program Memory on CLA
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PIE Channel Mapping
        1. 3.5.1.1 F2837x vs F28P65x PIE Channel Mapping Comparison
      2. 3.5.2 Bootrom
      3. 3.5.3 AGPIO Filter
    6. 3.6 Power Management
      1. 3.6.1 VREGENZ
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
      1. 3.8.1 F2837x vs F28P65x GPIO Mux Comparison
    9. 3.9 Analog Multiplexing Changes
      1. 3.9.1 F2837x_176PTP vs F28P65x_176PTP Analog Connections Comparison
  7. 4Application Code Migration From F2837x to F28P65x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5EABI Support
    1. 5.1 NoINIT Struct Fix (Linker Command)
    2. 5.2 Pre-Compiled Libraries
  9.   References

2.3 176-Pin PTP New PCB Design

To enable early development on F28P65x using existing F2837x 176-Pin device, this supplemental section covers the dual routing technique as illustrated in Figure 2-5. The complete pin usage recommendation is outlined in Figure 2-1.

GUID-20220607-SS0I-GTDV-BDVW-ZDLZTLML0WJC-low.svg Figure 2-4 Dual Routing Technique Illustrated

For the color legend, see Figure 2-1.

Table 2-6 Common 176-Pin PTP PCB Design for F2837x and F28P65x
Pin No Pin Name Transition Type Action
F2837x F28P65x F2837x to F28P65x F28P65x to F2837x
Minor Incompatibility - Signals in Common
29 ADCINC4 ADCINC4/GPIO205 Common Analog Channel Use ADCINC4
30 ADCINC3 ADCINC3/GPIO206 Use ADCINC3
31 ADCINC2 ADCINC2/AIO237 Use ADCINC2
38 ADCINA5 ADCINA5/AIO232 Use ADCINA5
39 ADCINA4 ADCINA4/AIO231 Use ADCINA4
40 ADCINA3 ADCINA3/AIO230 Use ADCINA3
41 ADCINA2 ADCINA2/AIO229 Use ADCINA2
42 ADCINA1 ADCINA1/AIO228 Use ADCINA1
43 ADCINA0 ADCINA0/AIO227 Use ADCINA0
44 ADCIN14 ADCIN14/AIO225 Use ADCIN14
45 ADCIN15 ADCIN15/AIO226 Use ADCIN15
46 ADCINB0 ADCINB0/AIO233 Use ADCINB0
47 ADCINB1 ADCINB1/AIO234 Use ADCINB1
48 ADCINB2 ADCINB2/AIO235 Use ADCINB2
49 ADCINB3 ADCINB3/AIO236 Use ADCINB3
77 TDI GPIO222/TDI Common JTAG Use TDI
78 TDO GPIO223/TDO Use TDO
92 ERRORSTS GPIO224/ERRORSTS Common ERROR Pin Use ERRORSTS
Medium Incompatibility - Different Signals, Same Type
56 ADCIND0 ADCINB7 Analog Function Compatible Update code to ADCINB7 Update code to ADCIND0
57 ADCIND1 ADCINA6 Update code to ADCINA6 Update code to ADCIND1
58 ADCIND2 ADCINA7 Update code to ADCINA7 Update code to ADCIND2
59 ADCIND3 ADCINA8 Update code to ADCINA8 Update code to ADCIND3
60 ADCIND4 ADCINA9 Update code to ADCINA9 Update code to ADCIND4
Medium incompatibility - Dual routing (1)
22 GPIO22 ADCINC0/GPIO199 Dual PCB Route, through 0-Ohm Resistor or DNP to either GPIO channel or Power pin. Dual route (A) to Pin 22 and Pin 11
23 GPIO23 ADCINC9/GPIO200 Dual route (A) to Pin 23 and Pin 16
24 GPIO24 ADCINC8/GPIO201 Dual route (A) to Pin 24 and Pin 159
25 GPIO25 ADCINC7/GPIO202 Dual route (A) to Pin 25 and Pin 153
27 GPIO26 ADCINC6/GPIO203 Dual route (A) to Pin 27 and Pin 82
28 GPIO27 ADCINC5/GPIO204 Dual route (A) to Pin 28 and Pin 125
63 GPIO30 ADCINA11/GPIO214 Dual route (A) to Pin 63 and Pin 79, consult datasheet for F2837x TRSTn requirement
64 GPIO28 ADCINB4/GPIO215 Dual route (A) to Pin 64 and Pin 74
65 GPIO29 ADCINB5/GPIO216 Dual route (A) to Pin 65 and Pin 73
66 GPIO31 ADCINB8/GPIO217 Dual route (A) to Pin 66 and Pin 158
67 GPIO32 ADCINB9/GPIO218 Dual route (A) to Pin 67 and Pin 116
Medium incompatibility - Dual routing(1)
55 VREFHID ADCINB6 ADC VREFHI to Analog Populate 0 ohm resistor to ADCINB6 Populate 0 ohm resistor to VREFHID
51 VREFLOD ADCINB11 ADC VREFLO to Analog Populate 0 ohm resistor to ADCINB11 opulate 0 ohm resistor to VREFLOD
79 TRSTn GPIO30 TRSTn Function Populate 0 ohm resistor to GPIO30 Populate 0 ohm resistor to TRSTn
20 VDDIO GPIO106 Dual PCB Route, through 0-Ohm Resistor or DNP to GPIO/AGPIO channel or Power pin. Populate 0 ohm resistor to GPIO/AGPIO Populate 0 ohm resistor to VDDIO
106 VDDIO GPIO105
147 VDDIO GPIO104
20 VDDIO ADCINC1/GPIO198
68 VDDIO ADCINB10/GPIO219
61 VDD ADCINA10/GPIO213 Populate 0 ohm resistor to VDD
153 VDD GPIO25
158 VDD GPIO31
126 VDD GPIO103
74 FLT2 GPIO28 Dual PCB Route, through 0-Ohm Resistor or DNP to GPIO channel or FLT Populate 0 ohm resistor to GPIO channel Populate 0 ohm resistor to FLT pads
73 FLT1 GPIO29
1. Use Dual Routing example diagram (A) in Figure 2-5
1. Use Dual Routing example diagram (B) in Figure 2-5