If a user does not want to use the MSS_VIM_FIQVEC register, the VIM may be used as a more traditional interrupt controller. Note that in this mode, there is no hardware priority masking (because the MSS_VIM_FIQVEC register is never read). Software would be responsible for doing all priority operations.
- Determine which interrupt to service
- Read the MSS_VIM_PRIFIQ register to determine
which interrupt is the highest priority FIQ currently asserted, OR
- Optionally read the MSS_VIM_FIQGSTS register to determine which groups have IRQs pending, then read the MSS_VIM_FIQSTS_j register and use a software prioritization scheme to determine which FIQ to service
- Service the interrupt
- Depending on whether the original source of the interrupt was a pulse or a level
- Pulse
- Clear the status by writing a '1' to the appropriate bit in the MSS_VIM_STS_j register, or MSS_VIM_FIQSTS_j register
- Clear the interrupt at the source.
- Level
- Clear the interrupt at the source
- Clear the status by writing a '1' to the appropriate bit in the MSS_VIM_STS_j register, or MSS_VIM_FIQSTS_j register.