The proper sequence for resetting the
R5FSS is as follows:
- Set R5SSx_RST_ASSERDLY and MSS_RCM.R5SSx_RST2ASSERTDLY registers with
required reset asserting and holding delay.
- By default, the reset FSM (or
any reset to R5FSS[0-1]_CORE[0-1]) waits for CPU to go to WFI state for safe handling
of system. Setting R5SS[0-1]_FORCE_WFI_ CR5_WFI_OVERIDE to 7 overrides the
WFI check but this is not recommended.
- Set the corresponding reset bit field, refer to R5FSS
Reset for further details.
- Read the R5SS[0-1]_RST_STATUS_CAUSE register to know the status of the
initiated reset .
- Set R5SS[0-1]_RST_CAUSE_CLR_CLR register to reset the captured status of
R5SS[0-1]_RST_STATUS_CAUSE register.
Note: Care must be taken to read all the
R5SS[0-1]_RST_STATUS_CAUSE register status bits before clearing
them.
These resets do not reset the target and initiator ports as these are connected with
the common bus to the SoC interconnects. Use INFRA_RST_CTRL_ASSERT bit field to
reset the full SoC interconnect infrastructure. This is not recommended for use and
must only be used by the application code when there is no pending
transactions/tasks.