SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
A single GPMC0 module is integrated in the device. The diagram below provides a visual representation of the device integration details.
The tables below summarize the device integration details of GPMC0.
Module Instance | Device Allocation | SoC Interconnect |
---|---|---|
GPMC0 | ✓ | Core VBUSM Interconnect |
Module Instance | Module Clock Input | Source Clock Signal | Source | Default Freq | Description |
---|---|---|---|---|---|
GPMC0 | GPMC0_ICLK (CLK) | SYS_CLK | PLL_CORE_CLK: HSDIV0_CLKOUT0 | 200 MHz | GPMC0 Interface Clock |
GPMC0_FCLK | XTALCLK | External XTAL or RC Oscillator | 25 MHz | GPMC0 Functional Clock | |
EXT_REFCLK | External Reference Clock (EXT_REFCLK) | 100 MHz | |||
SYS_CLK | PLL_CORE_CLK: HSDIV0_CLKOUT0 | 200 MHz | |||
DPLL_PER_HSDIV0_CLKOUT1 | PLL_PER_CLK: HSDIV0_CLKOUT1 | 192 MHz | |||
DPLL_CORE_HSDIV0_CLKOUT0 (not supported) | PLL_CORE_CLK: HSDIV0_CLKOUT0 | 400 MHz | |||
RCCLK10M | Internal 10 MHz RC Oscillator (RCCLK10M) | 10 MHz | |||
WUCPUCLK | Oscillator Clock | 25 MHz | |||
RCCLK10M | Internal 10 MHz RC Oscillator (RCCLK10M) | 10 MHz |
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
---|---|---|---|---|
GPMC0 | GPMC0_RST | Warm Reset (MAIN_RST) | RCM + Warm Reset Sources | GPMC0 Asynchronous Reset |
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Type | Description |
---|---|---|---|---|---|
GPMC0 |
GPMC_SINTERRUPT_INTR |
GPMC_SINTERRUPT_INTR |
ALL R5FSS Cores | Level |
GPMC0 Interrupt Request |
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Type | Description |
---|---|---|---|---|---|
GPMC0 | GPMC0_SDMA |
GPMC0_SDMA_REQ |
EDMA Crossbar (EDMA_XBAR) | Level | GPMC0 DMA Request |
For more information on the interconnects, see the System Interconnect chapter.
For more information on power, reset, and clock management, see the corresponding sections within the Device Configuration chapter.
For more information on the device interrupt controllers, see the Interrupt Controllers chapter.
For more information on how to configure GPMC_CLK, see the Clocking section in Device Configuration chapter.