SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
This operation multiplies the vector value in src0 with the one in src1 and stores the result in tgt. The multiplication is done in the field GF(2m) defined by the content of the GF2M_POLYNOMIAL register (that is, registers GF2M_POLYNOMIAL_0 through GF2M_POLYNOMIAL_17), combined with the content of the GF2M_FIELDSIZE register. Squaring a value is supported by simply letting src0 and src1 refer to the same GF2M_OPERAND register (that is, registers GF2M_OPERAND_A_0 through GF2M_OPERAND_D_17).
Except for vectors that have the maximum field size (571), it is required that, for the MUL operation, vector values are loaded into their registers in shifted form. This means that the LSB of a vector value is not stored in bit 0 of the register, but in a higher bit position that depends on the actual field size and the multiplier depth. The LSB of the result in the target register will be in the same shifted position. For more details and background, see Section 3.4.4.1.6.4.1.1, GF(2m) Multiplications.
By nature of the used algorithm, the MUL operation works correctly even when the MSB of the prime polynomial (in GF2M_POLYNOMIAL register) is not set.