SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
The register GPMC_CONTROL configures the GPMC I/O clock source and GPMC feedback clock source, as shown in Figure 6-5.
GPMC_CONTROL.CLKOUT_SEL, when programmed to 0, selects the GPMC_FUNC_CLK from RCM as the I/O clock GPMC_CLK at the device pin. If a free running clock is desired at the device pin, the application must program this bit field to 0.
GPMC_CONTROL.CLKOUT_SEL, when programmed to 1, selects the divided clock from GPMC module as the I/O clock GPMC_CLK. In this case, the I/O clock is not free running and is only active during GPMC I/O transfers.
GPMC_CONTROL.CLK_LB_SEL configures the source of I/O loop back clock. Based on the system, timing, and noise careabouts, the application can configure the I/O loop back clock.
GPMC_CONTROL. CLK_OE_N and GPMC_CONTROL. CLK_LB_OE_N enable the output I/O buffer of GPMC_CLK and GPMC_LB_CLK.