SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
The receive CPDMA is an eight channel CPPI 3.0 compliant interface. Each channel has a single queue for frame reception. Priority between the eight queues may either be fixed or round robin as selected by FH_PTYPE in the CPDMA_Control register. If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest priority. Round robin priority proceeds from channel 0 to channel 7. Packet Data transfers occur on the TX_VBUSP interface in 64-byte maximum burst transfers. Any packet can be designated by the host to generate a host timesync event on Ethernet egress by setting the HOST_EVENT bit in the packet buffer descriptor.