SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
The memory ECC-related events from the event bus are aggregated in MSS_CTRL and exported to ESM for monitoring as shown in R5FSS Integration.
There are four ECC interrupts to the ESM that aggregate different categories of ECC events:
EVENT BUS Bit # | Description | Associated Status Register in MSS_CTRL |
---|---|---|
40 | ATCM single-bit ECC error |
R5SS*_CPU*_ECC_CORR_ERRAGG_STATUS[0] R5SS*_CPU*_ATCM_CORR_ERR |
42 |
B1TCM single-bit ECC error |
R5SS*_CPU*_ECC_CORR_ERRAGG_STATUS[1] R5SS*_CPU*_B1TCM_CORR_ERR |
41 |
B0TCM single-bit ECC error |
R5SS*_CPU*_ECC_CORR_ERRAGG_STATUS[2] R5SS*_CPU*_B0TCM_CORR_ERR |
24 |
Data cache tag or dirty RAM parity error or correctable ECC error, from data-side or ACP |
R5SS*_CPU*_ECC_CORR_ERRAGG_STATUS[3] R5SS*_CPU*_DTAG_CORR_ERR |
25 |
Data cache data RAM parity error or correctable ECC error |
R5SS*_CPU*_ECC_CORR_ERRAGG_STATUS[4] R5SS*_CPU*_DDATA_CORR_ERR |
22 |
Instruction cache tag RAM parity or correctable ECC error |
R5SS*_CPU*_ECC_CORR_ERRAGG_STATUS[5] R5SS*_CPU*_ITAG_CORR_ERR |
23 |
Instruction cache data RAM parity or correctable ECC error |
R5SS*_CPU*_ECC_CORR_ERRAGG_STATUS[6] R5SS*_CPU*_IDATA_CORR_ERR |
EVENT BUS Bit # | Description | Associated Status Register in MSS_CTRL |
---|---|---|
37 |
ATCM multi-bit ECC error |
R5SS*_CPU*_ECC_UNCORR_ERRAGG_STATUS[0] R5SS*_CPU*_ATCM_UNCORR_ERR |
39 |
B1TCM multi-bit ECC error |
R5SS*_CPU*_ECC_UNCORR_ERRAGG_STATUS[1] R5SS*_CPU*_B1TCM_UNCORR_ERR |
38 |
B0TCM multi-bit ECC error |
R5SS*_CPU*_ECC_UNCORR_ERRAGG_STATUS[2] R5SS*_CPU*_B0TCM_UNCORR_ERR |
34 |
Data caches tag/dirty RAM fatal ECC error, from data-side or ACP. |
R5SS*_CPU*_ECC_UNCORR_ERRAGG_STATUS[3] R5SS*_CPU*_DTAG_UNCORR_ERR |
33 |
Data cache data RAM fatal ECC error |
R5SS*_CPU*_ECC_UNCORR_ERRAGG_STATUS[4] R5SS*_CPU*_DDATA_UNCORR_ERR |