SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
Events mapped to the high priority error interrupt are intended to be events that require immediate intervention from the system because a potentially dangerous error has occurred. An example would be an event indicating an uncorrected error. The system will want to diagnose the issue and intervene to ensure there are no violations.
Any error event can be mapped to the high priority error interrupt. It is enabled by programming,
Write the correct value of the register by setting the event bit which needs to be monitored
Error Group N Interrupt Enabled Set Register (Base Address + 0x400 + N*0x20 + 0x08)
Set the respective field to 0x1 in Error Group N Interrupt Priority Register (Base Address + 0x400 + N*0x20 + 0x10) to map the events to high priority error interrupt
When a High Priority Error Interrupt is received, the acting processor should follow these steps:
Read the High Interrupt Status Register (Base Address + 0x24)
If both high_level_prio and high_pulse prio are equal to 0xFFFF, then END (Interrupt is no longer asserted)
If either high_level_pend or high_pulse_pend (or both) are not equal to 0xFFFF, software has two options for determining what event to service
First Option: Record the value of value in high_pulse_prio and/or high_level_prio. Determine which is higher priority. This is the Global Event Number of the highest priority High Priority Error Event
Read the High Priority Interrupt Status Register (Base Address + 0x2C) to determine which Event Group(s) have pending High Priority Interrupts
Read the desired Error Group N Interrupt Enabled Status/Clear Register (Base Address + 0x400 + N*0x20 + 0x04)
Service the Error Event based on the IP’s specification
Fixing the error
Resetting the peripheral that triggered the error
Resetting the device
Communicating outside the SoC for outside intervention
The rest of these steps assume that the Error has been handled and the system wants to clear the error event
The rest of the handling depends on whether the event is a pulse or level event
Level Event
Clear the Error Event at the Source
Write a 0x1 to the appropriate bit in the Error Group N Interrupt Enabled Status/Clear Register (Base Address + 0x400 + N*0x20 + 0x04)
This will clear the raw status
If the error event is still asserted (or re-asserted) the raw status will be set back to 1
If there are no error events, the level will de-assert.
Write the EOI vector to the EOI Interrupt Register (Base Address + 0x30)
If there are additional High Priority enabled error events pending, then a new pulse will be generated
If there are no additional High Priority enabled error events pending, there will be no new pulse
Write a CLEAR to the Error Pin Control Register (Base Address + 0x40)
This step is optional if the event is not enabled to influence the Error Pin (Error Group N Error Pin Influence Set Register (Base Address + 0x400 + N*0x20 + 0x14)), but may be done regardless as an extra CLEAR is not harmful
Pulse Event
Write a 0x1 to the appropriate bit in the Error Group N Interrupt Enabled Status/Clear Register (Base Address + 0x400 + N*0x20 + 0x04)
This will de-assert the level interrupt
Write the EOI vector to the EOI Interrupt Register (Base Address + 0x30)
If there are additional High Priority enabled error events pending, then a new pulse will be generated and the level interrupt will remain asserted
If there are no additional High Priority enabled error events pending, there will be no new pulse
The source may generate a new pulse which will show up as a new Error Event at the ESM
Write a CLEAR to the Error Pin Control Register (Base Address + 0x40)
This step is optional if the event is not enabled to influence the Error Pin (Error Group N Error Pin Influence Set Register (Base Address + 0x400 + N*0x20 + 0x14)), but may be done regardless as an extra CLEAR is not harmful