SPRUJ17H March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
IEP functional clock source selection:The clock source selection to the IEP module is done in register CTRLMMR_PRU_ICSS_CLKSEL[19-16] IEP_CLKSEL (where n = 0 or 1) in the CTRL_MMR0 location. For more information on these PRU-ICSS level input clocks, refer to the PRU-ICSS Integration.
Enhanced GPIO clock divider settings:In certain sample/shift clock settings of the PRU0 and PRU1 EGPIOs (when enabled in serial mode) two cascaded fractional dividers are done in the PRU_ICSS_CFG top level configuration registers PRU_ICSS_GPCFG0 and PRU_ICSS_GPCFG1. In addition, EGPIO clock active edge selection control can be exerted via the bit PRU0_GPI_CLK_MODE for PRU0 EGPIO and PRU1_GPI_CLK_MODE for the PRU1 EGPIO.