The ECC aggregator has ECC control, status and interrupt registers for each ECC endpoint in a module or subsystem. These registers are memory mapped and occupy 1 KB address space although part of it may contain reserved locations. The registers are split in the following types:
- Global registers. They are common to all ECC endpoints associated with the ECC aggregator and include the ECC_VECTOR and ECC_REV registers. Each ECC endpoint has assigned a unique ID. When this ID is written to the ECC_VECTOR[10-0] ECC_VECTOR field the corresponding endpoint is selected either for control or for status reading.
- ECC control and status registers. These registers are specific to each ECC
endpoint and reside in the range from address offset 0x10 to 0x24 for the ECC RAM
endpoint. They are memory mapped but are accessed through the ECC serial interface. They
are also selected by the ECC endpoint ID written to the ECC_VECTOR[10-0] ECC_VECTOR
field. Because of latency on the serial interface the ECC control and status registers
are read by performing special sequence as described in Section 13.6.2.3.3. These registers have also different functionality for types of ECC endpoints.
- Interrupt registers. They include interrupt status, interrupt enable,
interrupt disable, and EOI registers. For more information, see Section 13.6.2.3.5.