NAVSS0_RINGACC0 supports the following features:
- Supports independent memory-mapped ring structures. See ring count in Table 10-112, RINGACC Configuration Parameters.
- Supports various modes for each ring based on usage and compatability
- Provides single-word deep shared incoming Transfer Response FIFO
- Provides bit-wide source VBUSM read/write slave interface for accesses from DMA controller entities.
- Provides 2 word deep command FIFO
- Provides 2 word deep write data FIFO
- Provides 2 word deep read data FIFO
- Provides 2 word deep write status FIFO
- Provides bit-wide destination VBUSM
read/write master interface for accesses to ring structures in memory
- Supports up to 16 outstanding
writes
- Supports up to 16 outstanding
reads
- Source interface provides an array
of 1024 × 512-byte long address windows (four for each ring) which are packed
into a single contiguous address range
- Read and write addresses
which target a specific window are translated, in order to redirect the
read or write transaction, to an effective address calculated from the
base address for the ring plus current ring offset
- Each read or write access
presented on VBUSM slave interface is modified and bridged onto the
VBUSM master interface