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SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

12.6.3.8.5 DISPC VID Scaler Unit

Note:

Only VID pipeline includes a resizer unit (scaler). The VIDL pipeline does not include a scaler.

The programmable scaler filter works with all supported video formats, including formats with alpha channel. The alpha channel is scaled with the same parameters as the RGB color components. For the YUV formats, Y and Cb/Cr are processed independently. A RGB 64-bit source (16 bits per component) is truncated to 8-bit/compontent, if the scaler is enabled. Otherwise, it will be truncated to ARGB48 format in the scaler bypass mode. A 10-bit/12-bit YUV source is also truncated to 8-bit, since the scaler is enabled to either upsample the chroma component and/or resize the YUV frame data directly (for memory-to-memory operation with YUV format as the memory destination type).

The filter is based on a finite impulse response (FIR) filter with 16 phases. The filter is a 5-tap for horizontal filtering, and can be configured for 3 or 5 taps for vertical filtering. The filtering can be used for various processing:

Up-sampling of the picture
Down-sampling of the picture
Anti-aliasing reduction
Chrominance resampling in case of YUV data formats

The following limitations must be considered:

The up-sampling ratio is up to x16.
The down-sampling ratio using 3-tap configuration is down to x0.5 for RGB format.
The down-sampling ratio using 5-tap configuration is down to x0.25 for RGB format.

Note:

The user must set the correct size and position of the original video before resize in order for the up-sampled/down-sampled video to be displayed inside the screen boundaries.

Figure 12-339 shows an example of video up-sampling, with corresponding video window attributes.

Figure 12-339 DISPC Video Window Attributes

The video window attributes can be configured in the following register bit-fields:

Source data format (input to the scaler unit) in DSS0_VID_ATTRIBUTES[6-1] FORMAT bit-field
Video picture width in system memory (frame buffer) in DSS0_VID_PICTURE_SIZE[13-0] MEMSIZEX bit-field. The window width is from 1 up to 4096 pixels. All the integer values in the range [1:4096] are allowed except for YUV422 formats. In case of YUV2422 and UYVY422 formats the width has to be a multiple of 2 pixels.
Video picture height in system memory (frame buffer) in DSS0_VID_PICTURE_SIZE[29-16] MEMSIZEY bit-field. The window width is from 1 up to 4096 pixels. All the integer values in the range [1:4096] are allowed.
Video window width at pipeline output (after resizing) in DSS0_VID_SIZE[13-0] SIZEX bit-field. The window width is from 1 up to 4096 pixels. All the integer values in the range [1:4096] are allowed up to the screen width minus the horizontal start location of the window on the screen.
Video window height at pipeline output (after resizing) in DSS0_VID_SIZE[29-16] SIZEY bit-field. The window height is from 1 up to 4096 pixels. All the integer values in the range [1:4096] are allowed up to the screen height minus the vertical start location of the window on the screen.
Video window overlay X-position in DSS0_OVR_ATTRIBUTES2_0 through DSS0_OVR_ATTRIBUTES2_4[13-0] POSX bit-field. See Section 12.6.3.10, DISPC Overlay Managers.
Video window overlay Y-position in DSS0_OVR_ATTRIBUTES2 through DSS0_OVR_ATTRIBUTES2_4[29-16] POSY bit-field. See Section 12.6.3.10, DISPC Overlay Managers.
For configuration of LPP and PPL video port output display parameters, see Section 12.6.3.11.8, DISPC VP Timing Generator and Display Panel Settings.

For vertical up-sampling and down-sampling in a 3-tap configuration, the equations are:

Equation 23.

For vertical and horizontal up-sampling and down-sampling in a 5-tap configuration, the equations are:

Equation 24.

Note:

The pixel (n + 1) is the previous pixel with respect to pixel (n). The line (n + 1) is the previous line with respect to line (n).

The coefficients Ci() depend on the phase between input and output pixels.

The coefficients are different for Y and Cr/Cb filtering because the calculations are independent due to the chrominance resampling for YUV422 and YUV420.

First, the vertical filter is applied to the encoded input pixel data, and then the horizontal filter is applied on the resulting pixel values to generate the output pixel values. The vertical input of the filter consists of:

Six lines of 2048 × 32 bits for 5-tap configuration
Three lines of 4096 x 32 bits for 3-tap configuration

Table 12-340 lists some of the scaler supported configurations.

Table 12-340 DISPC VID Line Buffer Width for Scaler Unit

Pixel Format	Maximum Input Width (Pixels) for 5-tap	Maximum Input Width (Pixels) for 3-tap
32 bits per pixel (ARGB32-8888, ARGB-2101010, etc.)	2048 pixels wide ⁽¹⁾	4096 pixels wide
YUV420, YUV422	4096 pixels wide	4096 pixels wide

(1) For the 5-tap configuration, the 6th video line is used on the output of the horizontal scaler in order to start the next output line generation while the video pipeline output is being stalled by the overlay manager (either due to display in blanking period and/or in background pixel period). The 6th line buffer is actually 48-bit wide to allow storage of ARGB48 format pixel data.

At the beginning of frame scaling processing, the first line may be duplicated multiple times depending on the initial vertical phase programmed for the poly-phase filter.

At the end of frame scaling processing the last line is duplicated, if the scaling logic requires loading more lines and the last line has been reached.

Similarly, the first pixel may be duplicated multiple times depending on the initial horizontal phase programmed for the poly-phase filter. The last pixel is duplicated, if the scaling logic requires loading more pixels and the last pixel has been reached.

The programmable coefficients of the polyphase filters are signed 10-bit values (except for the central coefficient, which is unsigned). The vertical video scaler has an 10-bit input and a 12-bit output. The horizontal scaling stage takes the resulting 12-bit input and produces 12-bit output.

Figure 12-340 and Figure 12-341 show the scaler macro-architecture for components A, R, G, and B. Figure 12-342 and Figure 12-343 show the scaler macro-architecture for components Y, Cr, and Cb.

Note:

The scaling and CSC clipping is set by the same bit, DSS0_VID_ATTRIBUTES[11] FULLRANGE.

Figure 12-340 DISPC VID Macro-Architecture of the Horizontal Scaling for A, R, G, and B Components (5-tap Restriction)

Figure 12-341 DISPC VID Macro-Architecture of the Vertical Scaling for A, R, G, and B Components (5 and 3 taps)

Figure 12-342 DISPC VID Macro-Architecture of the Horizontal Scaling for Y, Cr, and Cb Components (5-tap Restriction)

Figure 12-343 DISPC VID Macro-Architecture of the Vertical Scaling for Y, Cr, and Cb Components (5 and 3 taps)

Table 12-341 list the register fields in the function of the coefficients for the VID horizontal scaler in the DSS0_VID_FIR_COEF_H0_0 to DSS0_VID_FIR_COEF_H0_8, and DSS0_VID_FIR_COEF_H12_0 to DSS0_VID_FIR_COEF_H12_15 registers.

Table 12-341 DISPC Register Fields Associated to Coefficients for ARGB and Y Configuration in VID Horizontal Scaler

Phases	Ch(2)	Ch(1)	Ch(0)	Ch(-1)	Ch(-2)
	Signed coefficient [29-20] FIRHC2 bitfield	Signed coefficient [19-10] FIRHC1 bitfield	Unsigned central coefficient [9-0] FIRHC0 bitfield	Signed coefifcient [19-10] FIRHC1 bitfield	Signed coefficient [29-20] FIRHC2 bitfield
0	DSS0_VID_FIR_COEF_H12_0	DSS0_VID_FIR_COEF_H12_0	DSS0_VID_FIR_COEF_H0_0	DSS0_VID_FIR_COEF_H12_0	DSS0_VID_FIR_COEF_H12_0
1	DSS0_VID_FIR_COEF_H12_1	DSS0_VID_FIR_COEF_H12_1	DSS0_VID_FIR_COEF_H0_1	DSS0_VID_FIR_COEF_H12_15	DSS0_VID_FIR_COEF_H12_15
2	DSS0_VID_FIR_COEF_H12_2	DSS0_VID_FIR_COEF_H12_2	DSS0_VID_FIR_COEF_H0_2	DSS0_VID_FIR_COEF_H12_14	DSS0_VID_FIR_COEF_H12_14
3	DSS0_VID_FIR_COEF_H12_3	DSS0_VID_FIR_COEF_H12_3	DSS0_VID_FIR_COEF_H0_3	DSS0_VID_FIR_COEF_H12_13	DSS0_VID_FIR_COEF_H12_13
4	DSS0_VID_FIR_COEF_H12_4	DSS0_VID_FIR_COEF_H12_4	DSS0_VID_FIR_COEF_H0_4	DSS0_VID_FIR_COEF_H12_12	DSS0_VID_FIR_COEF_H12_12
5	DSS0_VID_FIR_COEF_H12_5	DSS0_VID_FIR_COEF_H12_5	DSS0_VID_FIR_COEF_H0_5	DSS0_VID_FIR_COEF_H12_11	DSS0_VID_FIR_COEF_H12_11
6	DSS0_VID_FIR_COEF_H12_6	DSS0_VID_FIR_COEF_H12_6	DSS0_VID_FIR_COEF_H0_6	DSS0_VID_FIR_COEF_H12_10	DSS0_VID_FIR_COEF_H12_10
7	DSS0_VID_FIR_COEF_H12_7	DSS0_VID_FIR_COEF_H12_7	DSS0_VID_FIR_COEF_H0_7	DSS0_VID_FIR_COEF_H12_9	DSS0_VID_FIR_COEF_H12_9
8	DSS0_VID_FIR_COEF_H12_8	DSS0_VID_FIR_COEF_H12_8	DSS0_VID_FIR_COEF_H0_8	DSS0_VID_FIR_COEF_H12_8	DSS0_VID_FIR_COEF_H12_8
9	DSS0_VID_FIR_COEF_H12_9	DSS0_VID_FIR_COEF_H12_9	DSS0_VID_FIR_COEF_H0_7	DSS0_VID_FIR_COEF_H12_7	DSS0_VID_FIR_COEF_H12_7
10	DSS0_VID_FIR_COEF_H12_10	DSS0_VID_FIR_COEF_H12_10	DSS0_VID_FIR_COEF_H0_6	DSS0_VID_FIR_COEF_H12_6	DSS0_VID_FIR_COEF_H12_6
11	DSS0_VID_FIR_COEF_H12_11	DSS0_VID_FIR_COEF_H12_11	DSS0_VID_FIR_COEF_H0_5	DSS0_VID_FIR_COEF_H12_5	DSS0_VID_FIR_COEF_H12_5
12	DSS0_VID_FIR_COEF_H12_12	DSS0_VID_FIR_COEF_H12_12	DSS0_VID_FIR_COEF_H0_4	DSS0_VID_FIR_COEF_H12_4	DSS0_VID_FIR_COEF_H12_4
13	DSS0_VID_FIR_COEF_H12_13	DSS0_VID_FIR_COEF_H12_13	DSS0_VID_FIR_COEF_H0_3	DSS0_VID_FIR_COEF_H12_3	DSS0_VID_FIR_COEF_H12_3
14	DSS0_VID_FIR_COEF_H12_14	DSS0_VID_FIR_COEF_H12_14	DSS0_VID_FIR_COEF_H0_2	DSS0_VID_FIR_COEF_H12_2	DSS0_VID_FIR_COEF_H12_2
15	DSS0_VID_FIR_COEF_H12_15	DSS0_VID_FIR_COEF_H12_15	DSS0_VID_FIR_COEF_H0_1	DSS0_VID_FIR_COEF_H12_1	DSS0_VID_FIR_COEF_H12_1

Note:

In Table 12-341, the cells without color are duplicated from the grey cells.

Similar table approach applies to the vertical scaler (registers DSS0_VID_FIR_COEF_V0_0 to DSS0_VID_FIR_COEF_V0_8, and DSS0_VID_FIR_COEF_V12_0 to DSS0_VID_FIR_COEF_V12_15 are used).

Similar table approach applies to the coefficients for Cb/Cr filtering in case of YUV format (registers DSS0_VID_FIR_COEF_H0_C_0 to DSS0_VID_FIR_COEF_H0_C_8, and DSS0_VID_FIR_COEF_H12_C_0 to DSS0_VID_FIR_COEF_H12_C_15, and DSS0_VID_FIR_COEF_V0_C_0 to DSS0_VID_FIR_COEF_V0_C_8 and DSS0_VID_FIR_COEF_V12_C_0 to DSS0_VID_FIR_COEF_V12_C_15 are used) .

The VID scaler unit vertical and/or horizontal sampling is selected by configuring the DSS0_VID_ATTRIBUTES[8-7] RESIZEENABLE bit field.

Prior to enabling the video up/down-sampling block a valid configuration has to be set by the user. After configuring the required VID registers change the DSS0_VP_CONTROL[5] GOBIT register bit of the video port the video pipeline is associated with. The software has to wait before setting the GO bit that the hardware has reset the bit. The software reset is not recommended since the application cannot guarantee to be able to reset it before the HW.

The following fields define the configuration of the video up-sampling/down-sampling block in the VID pipeline for ARGB and YUV formats:

Vertical upsampling and downsampling increment value in the [23-0] FIRVINC bit field of DSS0_VID_FIRV (for ARGB and Y) and DSS0_VID_FIRV2 (for CbCr) registers. The unsigned integer value range is 2²³. Software calculates the value using the following equation:
Horizontal upsampling and downsampling increment value in the [23-0] FIRHINC bit field of the DSS0_VID_FIRH (for ARGB and Y) and DSS0_VID_FIRH2 (for CbCr) registers. The unsigned integer value range is [1:16384]. Software calculates the value using the following equation:
Vertical up/downsampling accumulator value in the [23-0] VERTICALACCU bit field of the DSS0_VID_ACCUV_0 and DSS0_VID_ACCUV_1 (for ARGB and Y), and DSS0_VID_ACCUV2_0 and DSS0_VID_ACCUV2_1 (for CbCr) registers. The accumulator value indicates on which phase the vertical filtering starts. The DSS0_VID_ACCUV_0 register is used for progressive output, while for interlace output both DSS0_VID_ACCUV_0 and DSS0_VID_ACCUV_1 registers are used. The DSS0_VID_ACCUV2_0 and DSS0_VID_ACCUV2_1 registers are used in the same manner for progressive or interlace output.
Vertical upsampling and downsampling line buffer configuration via the DSS0_VID_ATTRIBUTES[21] VERTICALTAPS bit: The default value at reset time is 0x0 (3-tap configuration is used). If the bit field is reset, the 3-tap configuration is used.
Horizontal upsampling and downsampling accumulator value in the [23-0] HORIZONTALACCU bit field of the DSS0_VID_ACCUH_0 and DSS0_VID_ACCUH_1 (for ARGB and Y), and DSS0_VID_ACCUH2_0 and DSS0_VID_ACCUH2_1 (for CbCr) registers. The accumulator value indicates on which phase the horizontal filtering starts. The register DSS0_VID_ACCUH_0 is used for progressive output, while for interlace output both DSS0_VID_ACCUH_0 and DSS0_VID_ACCUH_1 registers are used. The DSS0_VID_ACCUH2_0 and DSS0_VID_ACCUH2_1 are used in the same manner for progressive or interlace output.

Table 12-342 lists the scaler vertical and horizonatal accumulator values and phases.

Table 12-342 DISPC VID Scaler Vertical and Horizontal Accumulator Phases

Accumulator Value (MSB bits)	Phases f
0	0
256 or -3840	1
512 or -3584	2
768 or -3328	3
1024 or -3072	4
1280 or -2816	5
1536 or -2560	6
1792 or -2304	7
2048 or -2048	8
2304 or -1792	9
2560 or -1536	10
2816 or -1280	11
3072 or -1024	12
3328 or -768	13
3584 or -512	14
3840 or -256	15

Vertical upsampling and downsampling central coefficients:
- For ARGB and Y, the vertical upsampling and downsampling central coefficients are defined in the DSS0_VID_FIR_COEF_V0_0 to DSS0_VID_FIR_COEF_V0_8 registers. There are 9 registers for the 16 phases with 1 coefficient for each of them. Symetrical implementation is used, so only 9 coefficients are used. Each register contains one 10-bit unsigned coefficient (the central one).
- Four CbCr, the vertical upsampling and downsampling central coefficients are set in DSS0_VID_FIR_COEF_V0_C_0 to DSS0_VID_FIR_COEF_V0_C_8 registers.
Vertical upsampling and downsampling coefficients:
- For ARGB and Y, the vertical upsampling and downsampling coefficients are defined in the DSS0_VID_FIR_COEF_V12_0 to DSS0_VID_FIR_COEF_V12_15 registers. There are 16 registers for the 16 phases with 2 coefficient for each of them, so a total of 32 programmable coefficients for the vertical up/down-sampling block. Each register contains two 10-bit signed coefficients.
- Four CbCr, the vertical upsampling and downsampling coefficients are set in DSS0_VID_FIR_COEF_V12_C_0 to DSS0_VID_FIR_COEF_V12_C_15 registers.
Horizontal upsampling and downsampling central coefficients:
- For ARGB and Y, the horizontal upsampling and downsampling central coefficients are defined in the DSS0_VID_FIR_COEF_H0_0 to DSS0_VID_FIR_COEF_H0_8 registers. There are 9 registers for the 16 phases with 1 coefficient for each of them. Symetrical implementation is used, so only 9 coefficients are used. Each register contains one 10-bit unsigned coefficient (the central one).
- Four CbCr, the horizontal upsampling and downsampling central coefficients are set in DSS0_VID_FIR_COEF_H0_C_0 to DSS0_VID_FIR_COEF_H0_C_8 registers.
Horizontal upsampling and downsampling coefficients:
- For ARGB and Y, the horizontal upsampling and downsampling coefficients are defined in the DSS0_VID_FIR_COEF_H12_0 to DSS0_VID_FIR_COEF_H12_15 registers. There are 16 registers for the 16 phases with 2 coefficient for each of them, so a total of 32 programmable coefficients for the horizontal up/down-sampling block. Each register contains two 10-bit signed coefficients.
- Four CbCr, the horizontal upsampling and downsampling coefficients are set in DSS0_VID_FIR_COEF_H12_C_0 to DSS0_VID_FIR_COEF_H12_C_15 registers.

The YUV filtering is based on the equations of the ARGB filtering. In addition to the registers used for ARGB filtering configuration, a second set of registers for filtering is used. The first set of registers is used for Y configuration (instead of ARGB configuration) and the second set of registers is used for CbCr filtering configuration. The two sets of registers can be the same when the YUV format is not converted to RGB after filtering. When the RGB conversion is required after filtering, then the chrominance needs to be re-sampled with a different filtering configuration because:

Chrominance samples are offset to the luminance samples. That is, DSS0_VID_FIRH2 and DSS0_VID_FIRV2, and DSS0_VID_ACCUV2_0/DSS0_VID_ACCUV2_1 and DSS0_VID_ACCUH2_0/DSS0_VID_ACCUH2_1 registers need to be configured differently than DSS0_VID_FIRH and DSS0_VID_FIRV, and DSS0_VID_ACCUH_0/DSS0_VID_ACCUH_1 and DSS0_VID_ACCUV_0/DSS0_VID_ACCUV_1 registers used for the luminance filtering.
Chrominance is sub-sampled by two horizontally only in case of YUV422, and horizontally and vertically in case of YUV420. The coefficients for the vertical chrominance re-sampling are identical to the coefficients for vertical luminance filtering in case of YUV422. The coefficients for the horizontal and vertical chrominance re-sampling are different than the ones for luminance filtering in case of YUV420.