SPRUJ28E November 2021 – September 2024 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Each video port output has a dedicated timing generator supporting progressive and interlaced modes. It is clocked using the pixel clock and is configured to generate the video data and sync signals to match the desired video display standard timings.
Two-level configuration for enabling the video ports exists:
Both ENABLE and VP_ENABLE register fields must be set in order for a VP (timing generator) to start.
Figure 12-367 shows the timing generator display parameters.
The width of VP output data bus is configured in the DSS0_VP_CONTROL[10-8] DATALINES register field, when TDM feature is disabled. When TDM is enabled, the width of the output data bus is defined according to Section 12.6.3.11.6, DISPC VP Multiple Cycle Output Format (TDM).
The size of the display panel is defined by:
Standard HSYNC/VSYNC timing generation is programmable as follows:
When the output is in BT.1120 or BT.656 mode, the following timing constants are mapped onto the DSS0_VP_TIMING_H and DSS0_VP_TIMING_V registers:
Horizontal/vertical synchronization and output enable signals polarity are programmable by setting the DSS0_VP_POL_FREQ[12] IVS, [13] IHS, and [15] IEO register bits. These signals can be gated by setting the DSS0_VP_CONFIG[7] VSYNCGATED and [6] HSYNCGATED register bits. In addition, the alignment between VSYNC and HSYNC signals can be programmed via the DSS0_VP_POL_FREQ[18] ALIGN register bit.
The latch of data can be driven on the rising or falling edge of the pixel clock by setting the DSS0_VP_POL_FREQ[14] IPC register bit. The drive of the SYNC and VSYNC signals in the function of the pixel clock is done by setting the DSS0_VP_POL_FREQ[16] RF bit.
Each VP output can be configured in progressive output mode or interlaced output mode. The selection is done by writing into the bit-field DSS0_VP_CONFIG[22] OUTPUTMODEENABLE register bit. The default setting is for progressive mode. The selection can be changed only when the corresponding VP output is disabled. The configuration is independent for each VP output. It is possible to change the configuration of one of the VP outputs while the other VP is enabled.
The pixel clock for each VP output can be gated by setting the DSS0_VP_CONFIG[5] PIXELCLOCKGATED register bit.
The hold time of the pixels on the data bus is determined in clock cycles by the DSS0_VP_CONTROL[16-14] HT register field.