6 Revision History
Changes from December 15, 2023 to October 10, 2024 (from Revision D (December 2023) to Revision E (October 2024))
- Updated Note on Register NamesGo
- (Memory Map): Added notes [6] and [7] for GPIO and WWDT access by
R5F cores.Go
- (Memory Map): Changed the following region names: TPCC0 → TPCC_A,
TPTC00 → TPTC_A0, TPTC01 → TPTC_A1Go
- (Memory Map): References to ICSSM updated to ICSS.Go
Changes from December 15, 2022 to December 15, 2023 (from Revision C (December 2022) to Revision D (December 2023))
- Updated Core Specific Memory Map 0x0000 0000 0x1FFF FFFF from 537 to
512Mb Go
- Added Lockstep versus Dual Core End Address and Size for TCMA and TCMB of each Core.Go
- Fixed incorrect end address locations for CORE0_TCMA_ROM, CORE0_TCMB_RAM, and CORE1_TCMB_RAMGo
- Further clarified end address and sizes based on lockstep versus dual coreGo
- Added table section to cover ROM to RAM swapGo
- AM263x TRM refinement - remove mention of CTRLMMR, change to sub-topic of Control Overview, add note below table.Go
Changes from October 1, 2022 to December 15, 2022 (from Revision B (October 2022) to Revision C (December 2022))
- Including AM263x collateral linksGo
- Updated PRU-ICSS Data RAM2 End Address from 0x0000 FFFF to 0x0001 FFFFGo
- Updated table vertical alignment. Updated descriptive text to prevent confusion.Go
- Lock/Kick protection register unlock values addedGo
- Adding note regarding CONTROLSS 16-bit register access requirementsGo