SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

17.2.50.1 MPU_16_PROGRAMMABLE_15_MPPA Register (Offset = 2E8h) [reset = 0h]

Programmable_15_MPPA.

Table 5-2001 Instance Table

Instance Name	Physical Address
MPU_R5SS0_CORE1_AHB	401E 02E8h

Figure 5-986 MPU_16_PROGRAMMABLE_15_MPPA Name Register

Table 5-2002 MPU_16_PROGRAMMABLE_15_MPPA Register Field Descriptions

Bit	Field	Type	Reset	Description
31:29	RESERVED3	R	0h	Always read as 0
28	LOCK	R/W	0h	this field is used for locking the corresponding MPU region configurations. Write 1 to lock the configurations along with the lock bit. Writing 1 is alllowed once per boot. Lock bit will clear on reset only. Once locked SW can not modify the MPU configurations along with lock bit.
27:26	RESERVED2	R	0h	Always read as 0.
25:10	AID15_0	R/W	0h	AIDs checked for this region. Defaults to input value. 0 = AID is not checked for these permissions. 1 = AID is checked for these permissions.
9	AIDX	R/W	0h	Additional AIDs checked. Defaults to input value.
8	RESERVED1	R	0h	Always read as 0.
7	NS	R/W	0h	Non-secure permission. Defaults to input value.
6	EMU	R/W	0h	Debug permission. Defaults to input value.
5	SR	R/W	0h	Supervisor read permission. Defaults to input value.
4	SW	R/W	0h	Supervisor write permission. Defaults to input value.
3	SX	R/W	0h	Supervisor executable permission. Defaults to input value.
2	UR	R/W	0h	User read permission. Defaults to input value.
1	UW	R/W	0h	User write permission. Defaults to input value.
0	UX	R/W	0h	User executable permission. Defaults to input value.