SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.8.1 ECC_AGGR_ERROR_STATUS1 Register (Offset = 20h) [reset = 0h]

ECC Error Status1 Register.

Table 5-901 Instance Table

Instance Name	Physical Address
ECC_AGGR	5301 0020h

Figure 5-449 ECC_AGGR_ERROR_STATUS1 Name Register

Table 5-902 ECC_AGGR_ERROR_STATUS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:16	ECC_BIT1	R	0h	Data bit that corresponds to the single-bit error
15	CLR_CTRL_REG_ERR	R/W1TC	0h	Clear control reg error Error Status, you must also re write the contorl ergister itself to clear this
14:13	CLR_PARITY_ERR	R/WD	0h	Clear parity Error Status
12	CLR_ECC_OTHER	R/W1TC	0h	Clear other Error Status
11:10	CLR_ECC_DED	R/WD	0h	Clear Double Bit Error Status
9:8	CLR_ECC_SEC	R/WD	0h	Clear Single Bit Error Status
7	CTR_REG_ERR	R/W1TS	0h	control register error pending, Level interrupt
6:5	PARITY_ERR	R/W1TS	0h	Level parity error Error Status
4	ECC_OTHER	R/W1TS	0h	Successive single-bit errors have occurred while a writeback is still pending, Level interrupt
3:2	ECC_DED	R/WI	0h	Level Double Bit Error Status
1:0	ECC_SEC	R/WI	0h	Level Single Bit Error Status