SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Interrupt Enable Set Register 0
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Instance Name | Physical Address |
---|---|
ECC_AGGR | 5301 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TPTC_A1_ENABLE_SETT | TPTC_A0_ENABLE_SET | MSS_MBOX_ENABLE_SET | MSS_L2SLV2_ENABLE_SET | RESERVED | MSS_L2SLV1_ENABLE_SET | MSS_L2SLV0_ENABLE_SET |
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | NONE | R/W1TS | R/W1TS |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:7 | RESERVED | NONE | 0h | Reserved |
6 | TPTC_A1_ENABLE_SETT | R/W1TS | 0h | Interrupt Enable Set Register for tptc_a1_pend |
5 | TPTC_A0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for tptc_a0_pend |
4 | MSS_MBOX_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mss_mbox_pend |
3 | MSS_L2SLV2_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mss_l2slv2_pend Interrupt Enable Set Register for mss_l2slv3_pend |
2 | RESERVED | NONE | 0h | Reserved |
1 | MSS_L2SLV1_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mss_l2slv1_pend |
0 | MSS_L2SLV0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mss_l2slv0_pend |