SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register is used to configure corresponding R5SS in Lock step or Dual core mode. The mode change can be affected only once in a SOC power cycle.
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Instance Name | Physical Address |
---|---|
MSS_CTRL | 50D0 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | R5SS1_CONTROL_RESET_FSM_TRIGGER | ||||||
NONE | R/W | ||||||
0h | 0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | R5SS1_CONTROL_LOCK_STEP_SWITCH_WAIT | ||||||
NONE | R/W | ||||||
0h | 7h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | R5SS1_CONTROL_LOCK_STEP | ||||||
NONE | R/W | ||||||
0h | 7h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:19 | RESERVED | NONE | 0h | Reserved |
18:16 | R5SS1_CONTROL_RESET_FSM_TRIGGER | R/W | 0h | Write pulse bit field: Writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit |
15:11 | RESERVED | NONE | 0h | Reserved |
10:8 | R5SS1_CONTROL_LOCK_STEP_SWITCH_WAIT | R/W | 7h | Writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch. |
7:3 | RESERVED | NONE | 0h | Reserved |
2:0 | R5SS1_CONTROL_LOCK_STEP | R/W | 7h | Writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if corresponding R5SS_CONTROL_LOCK_STEP_SWITCH_WAIT is set. Or else the switiching to Dual-core happens on the fly. |