SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register selects which R5 CPU when debug halted shall halt I2C[x] Peripheral.
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Instance Name | Physical Address |
---|---|
MSS_CTRL | 50D0 0444h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | I2C0_HALTEN_CR5B1_HALTEN | I2C0_HALTEN_CR5A1_HALTEN | I2C0_HALTEN_CR5B0_HALTEN | I2C0_HALTEN_CR5A0_HALTEN | |||
NONE | R/W | R/W | R/W | R/W | |||
0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:4 | RESERVED | NONE | 0h | Reserved |
3 | I2C0_HALTEN_CR5B1_HALTEN | R/W | 0h | 1'b0: IP Halt disabled with corresponding CPU halt 1'b1: IP Halt enabled with corresponding CPU halt |
2 | I2C0_HALTEN_CR5A1_HALTEN | R/W | 0h | 1'b0: IP Halt disabled with corresponding CPU halt 1'b1: IP Halt enabled with corresponding CPU halt |
1 | I2C0_HALTEN_CR5B0_HALTEN | R/W | 0h | 1'b0: IP Halt disabled with corresponding CPU halt 1'b1: IP Halt enabled with corresponding CPU halt |
0 | I2C0_HALTEN_CR5A0_HALTEN | R/W | 0h | 1'b0: IP Halt disabled with corresponding CPU halt 1'b1: IP Halt enabled with corresponding CPU halt |