SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.2.81 MSS_CTRL_MSS_TPCC_A_INTAGG_MASK Register

2.2.81.1 MSS_CTRL_MSS_TPCC_A_INTAGG_MASK Register (Offset = 830h) [reset = 0h]

This register Masks selected interrupt soures from the Aggregated TPCC0 interrupt.

Table 2-163 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D0 0830h

Figure 2-81 MSS_CTRL_MSS_TPCC_A_INTAGG_MASK Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED						MSS_TPCC_A_INTAGG_MASK_TPTC_A1	MSS_TPCC_A_INTAGG_MASK_TPTC_A0
NONE						R/W	R/W
0h						0h	0h
15	14	13	12	11	10	9	8
RESERVED							MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT7
NONE							R/W
0h							0h
7	6	5	4	3	2	1	0
MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT6	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT5	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT4	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT3	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT2	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT1	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT0	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INTG
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 2-164 MSS_CTRL_MSS_TPCC_A_INTAGG_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED	NONE	0h	Reserved
17	MSS_TPCC_A_INTAGG_MASK_TPTC_A1	R/W	0h	Mask Interrupt from TPTC A1 to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
16	MSS_TPCC_A_INTAGG_MASK_TPTC_A0	R/W	0h	Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
15:9	RESERVED	NONE	0h	Reserved
8	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT7	R/W	0h	Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
7	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT6	R/W	0h	Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
6	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT5	R/W	0h	Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
5	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT4	R/W	0h	Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
4	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT3	R/W	0h	Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
3	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT2	R/W	0h	Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
2	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT1	R/W	0h	Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
1	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INT0	R/W	0h	Mask Interrupt from TPCC A to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked
0	MSS_TPCC_A_INTAGG_MASK_TPCC_A_INTG	R/W	0h	Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG 1'b1 : Interrupt is Masked 1'b0 : Interrupt is Unmasked