SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.2.112 MSS_CTRL_MPU_ADDR_INTR_ERRAGG1_STATUS Register

2.2.112.1 MSS_CTRL_MPU_ADDR_INTR_ERRAGG1_STATUS Register (Offset = 8024h) [reset = 0h]

This register shows the Status of Unmasked MPU Address Errors to R5SS0 CORE1 .

Table 2-225 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D0 8024h

Figure 2-112 MSS_CTRL_MPU_ADDR_INTR_ERRAGG1_STATUS Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED						MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_HSM_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5B1_AHB_ADDR_ERR1
NONE						R/W	R/W
0h						0h	0h
15	14	13	12	11	10	9	8
MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5A1_AHB_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5B0_AHB_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5A0_AHB_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_SCRM2SCRP1_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_SCRM2SCRP0_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_QSPI_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_MBOX_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_DTHE_A_ADDR_ERR1
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5B1_AXIS_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5A1_AXIS_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5B0_AXIS_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5A0_AXIS_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_L2_BANK_D_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_L2_BANK_C_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_L2_BANK_B_ADDR_ERR1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_L2_BANK_A_ADDR_ERR1
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 2-226 MSS_CTRL_MPU_ADDR_INTR_ERRAGG1_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED	NONE	0h	Reserved
17	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_HSM_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
16	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5B1_AHB_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
15	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5A1_AHB_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
14	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5B0_AHB_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
13	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5A0_AHB_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
12	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_SCRM2SCRP1_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
11	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_SCRM2SCRP0_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
10	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_QSPI_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
9	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_MBOX_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
8	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_DTHE_A_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
7	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5B1_AXIS_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
6	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5A1_AXIS_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
5	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5B0_AXIS_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
4	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_CR5A0_AXIS_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
3	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_L2_BANK_D_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
2	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_L2_BANK_C_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
1	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_L2_BANK_B_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.
0	MPU_ADDR_INTR_ERRAGG1_STATUS_MPU_L2_BANK_A_ADDR_ERR1	R/W	0h	Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASK Wrie 0x1 to clear this Error.