SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.190.1 MSS_CTRL_TCM0_PARITY_ERRFRC Register (Offset = 1813Ch) [reset = 0h]

This register is used to Inject fault in the TCM Address Parity Error detection logic of R5SS0 .

Table 2-381 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D1 813Ch

Figure 2-190 MSS_CTRL_TCM0_PARITY_ERRFRC Name Register

Table 2-382 MSS_CTRL_TCM0_PARITY_ERRFRC Register Field Descriptions

Bit	Field	Type	Reset	Description
31:23	RESERVED	NONE	0h	Reserved
22:20	TCM0_PARITY_ERRFRC_B1TCM1	R/W	0h	Write pulse bit field: Writing 3'b111 forces a parity error for B1TCM of CR5B
19	RESERVED	NONE	0h	Reserved
18:16	TCM0_PARITY_ERRFRC_B1TCM0	R/W	0h	Write pulse bit field: Writing 3'b111 forces a parity error for B1TCM of CR5A
15	RESERVED	NONE	0h	Reserved
14:12	TCM0_PARITY_ERRFRC_B0TCM1	R/W	0h	Write pulse bit field: Writing 3'b111 forces a parity error for B0TCM of CR5B
11	RESERVED	NONE	0h	Reserved
10:8	TCM0_PARITY_ERRFRC_B0TCM0	R/W	0h	Write pulse bit field: Writing 3'b111 forces a parity error for B0TCM of CR5A
7	RESERVED	NONE	0h	Reserved
6:4	TCM0_PARITY_ERRFRC_ATCM1	R/W	0h	Write pulse bit field: Writing 3'b111 forces a parity error for ATCM of CR5B
3	RESERVED	NONE	0h	Reserved
2:0	TCM0_PARITY_ERRFRC_ATCM0	R/W	0h	Write pulse bit field: Writing 3'b111 forces a parity error for ATCM of CR5A